View ML7074-004_8922804.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fedl7074-004-01 issue date: nov. 12, 2003 ML7074-004 voip codec 1/98 general description the ML7074-004 is a speech codec for voip. this lsi allows selection of g.729.a, or g.711 standard as a speech codec. the lsi is optimum for adding voip functions to tas, routers, etc., since it has the functions of an echo canceller for 32 ms delay, dtmf detection, tone detection, tone generation, etc. features ? single 3.3 v power supply operation (dv dd 0, 1, 2, av dd : 3.0 to 3.6 v) ? speech codec: selectable among g.729.a (8 kbps), g.711 (64 kbps) ? -law, and a-law supports plc (packet loss concealment) func tion conforming to itu- t g.711 appendix i ? echo canceller for 32 ms delay ? dtmf detect function ? tone detect function: 2 systems (1650 hz, 2100 hz: detect frequency can be changed.) ? tone generate function: 2 systems ? fsk generation function ? dial pulse detect function ? dial pulse transmit function ? internal 1-channel 16-bit timer ? built-in fifo buffers (640 bytes) for transferring transmit and receive data frame/dma (slave) interface selectable. ? master clock frequency: 4.096 mhz (crystal oscillation or external input) ? hardware or software power down operation possible. ? analog input/output type: two built-in input amplifiers two built-in output amplifiers, 10 k ? driving ? package: 64-pin plastic qfp (qfp64-p-1414-0.80-bk) ? ordering part number: ML7074-004ga
fedl7074-003-01 ML7074-004 2/98 block diagram echo canceller dtmf_rec + - aff d/a lpf g.729.a tone_gen0 (tonea/b) tx buffer0 rx buffer0 frame/dma controller intb a0-a7 control register 8b d0-d15 16b vre f csb rdb wrb fr0b fr1b ack0b ack1b ain1n gsx1 vfro0 avref osc power pll speech codec 10k ? 10k ? dvdd2 dgnd2 avdd agnd pdnb tst1 xi xo g.711 txgain rxgain dvdd1 dgnd1 dvdd0 dgnd0 tst2 tst3 ckgn mck sync(8khz) lpad gpad atts attr bus control unit center clip encoder g.729.a g.711 decoder dtmf_det int dtmf_det tx buffer1 rx buffer1 ain0n gsx0 10k ? ain0p linear pcm codec vfro1 10k ? stgain sync bclk pcmi pcmo tone_det1 tone1_det s/p p/s serial i/f tone0_det tone1_det gpi0 gpi1 gpo0 gpo1 tone_det0 tone0_det fsk_gen tst0 clksel amp0 amp1 amp2 amp3 sin rout sout rin a/d bpf codec dpgen dpdet cr16-b0(gpi0) cr17-b0(gpo0) dp_det dp_det timer dtmf_code[3:0] dtmf_code[3:0] tone_gen1 (tonec/d) g.711 encode r g.711 decoder fgen_flag fgen_flag
fedl7074-003-01 ML7074-004 3/98 pin assignment (top view) 64-pin plastic qfp 49 avref vfro0 vfro1 avdd 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dgnd0 dgnd1 tst3 tst2 tst1 tst0 pcmo pcmi bclk sync dvdd1 rdb wrb csb fr0b fr1b dvdd0 a0 a1 a2 a3 a4 a5 a6 a7 dgnd2 xi xo dvdd2 gpi0 gpi1 gpo0 gpo1 pdnb intb ack0b ack1b clksel ain1n gsx1 ain0p ain0n gsx0 agnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 l7074-004
fedl7074-003-01 ML7074-004 4/98 pin descriptions pin no. symbol i/o pdnb = ?0? description 1 tst1 i ?0? test control input 1: normally input ?0?. 2 tst0 i ?0? test control input 0: normally input ?0?. 3 pcmo o ?hi-z? pcm data output 4 pcmi i i pcm data input i clksel = ?0? pcm shift clock input 5 bclk i/o ?l? clksel = ?1? pcm shift clock output i clksel = ?0? pcm sync signal 8 khz input 6 sync i/o ?l? clksel = ?1? pcm sync signal 8 khz output 7 dv dd 0 ? ? digital power supply 8 ack0b i i transmit buffer dma access acknowledge signal input 9 ack1b i i receive buffer dma access acknowledge signal input 10 fr0b (dmarq0b) o?h? fr0b: (cr11-b7 = ?0?) transmit buffer frame signal output dmarq0b: (cr11-b7 = ?1?) transmit buffer dma access request signal output 11 fr1b (dmarq1b) o?h? fr1b: (cr11-b7 = ?0?) receive buffer frame signal output dmarq1b: (cr11-b7 = ?1?) receive buffer dma access request signal output 12 intb o ?h? interrupt request output ?l? level is output for about 1.0 ? s when an interrupt is generated. 13 csb i i chip select control input 14 rdb i i read control input 15 wrb i i write control input 16 dgnd0 ? i digital ground (0.0 v) 17 d0 i/o i data input/output 18 d1 i/o i data input/output 19 d2 i/o i data input/output 20 d3 i/o i data input/output 21 d4 i/o i data input/output 22 d5 i/o i data input/output 23 d6 i/o i data input/output 24 d7 i/o i data input/output 25 d8 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?). 26 d9 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?). 27 d10 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?). 28 d11 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?). 29 d12 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?). 30 d13 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?). 31 d14 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?). 32 d15 i/o i data input/output fix to input state when using in 8-bit bus access (cr11-b5 = ?1?).
fedl7074-003-01 ML7074-004 5/98 pin no. symbol i/o pdnb = ?0? description 33 dv dd 1 ? ? digital power supply 34 a0 i i address input 35 a1 i i address input 36 a2 i i address input 37 a3 i i address input 38 a4 i i address input 39 a5 i i address input 40 a6 i i address input 41 a7 i i address input 42 pdnb i ?0? power down input ?0?: power down reset ?1?: normal operation 43 clksel i i sync and bclk i/o control input ?0?: sync and bclk become inputs ?1?: sync and bclk become outputs 44 dgnd1 ? ? digital ground (0.0 v) 45 gpi0 i i general-purpose input pin 0 (5 v tolerant input) /secondary function: dial pulse detect input pin 46 gpi1 i i general-purpose input pin 1 (5 v tolerant input) 47 gpo0 o ?l? general-purpose output pin 0 (5 v tolerant output, can be pulled up externally) /secondary function: dial pulse transmit pin 48 gpo1 o ?l? general-purpose output pin 1 (5 v tolerant output, can be pulled up externally) 49 av dd ? ? analog power supply 50 ain0p i i amp0 non-inverted input 51 ain0n i i amp0 inverted input 52 gsx0 o ?hi-z? amp0 output (10 k ? driving) 53 gsx1 o ?hi-z? amp1 output (10 k ? driving) 54 ain1n i i amp1 inverted input 55 avref o ?l? analog signal ground (1.4 v) 56 vfro0 o ?hi-z? amp2 output (10 k ? driving) 57 vfro1 o ?hi-z? amp3 output (10 k ? driving) 58 agnd ? analog ground (0.0 v) 59 dgnd2 ? digital ground (0.0 v) 60 xi i i 4.096 mhz crystal oscillator i/f, 4.096 mhz clock input 61 xo o ?h? 4.096 mhz crystal oscillator i/f 62 dv dd 2 ? digital power supply 63 tst3 i ?0? test control input 3: normally input ?0?. 64 tst2 i ?0? test control input 2: normally input ?0?.
fedl7074-003-01 ML7074-004 6/98 absolute maximum ratings parameter symbol conditions rating unit analog power supply voltage vda ? ? 0.3 to 5.0 v digital power supply voltage v dd ? ? 0.3 to 5.0 v analog input voltage vain analog pins ? 0.3 to v dd + 0.3 v vdin1 normal digital pins ? 0.3 to v dd + 0.3 v digital input voltage vdin2 5 v tolerant pins ? 0.3 to 6.0 v storage temperature range tstg ? ? 55 to +150 ? c recommended operating conditions (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditions min. typ. max. unit analog power supply voltage vda ? 3.0 3.3 3.6 v digital power supply voltage v dd ? 3.0 3.3 3.6 v operating temperature range ta ? ? 20 ? 60 ? c vih1 digital input pins 2.0 ? v dd + 0.3 v digital high level input voltage vih2 gpi0 and gpi1 pins 2.0 ? 5.5 v digital low level input voltage vil digital pins ? 0.3 ? 0.8 v digital input rise time tir digital pins ? 2 20 ns digital input fall time tif digital pins ? 2 20 ns digital output load capacitance cdl digital pins ? ? 50 pf capacitance of bypass capacitor for avref cvref between avref and agnd 2.2+0.1 ? 4.7+0.1 ? f master clock frequency fmck mck ? 0.01% 4.096 +0.01% mhz pcm shift clock frequency fbclk bclk (at input) 64 ? 2048 khz pcm sync signal frequency fsync sync (at input) ? 8.0 ? khz clock duty ratio drclk mck, bclk (at input) 40 50 60 % tbs bclk to sync (at input) 100 ? ? ns pcm sync timing tsb sync to bclk (at input) 100 ? ? ns pcm sync signal width tws sync (at input) 1bclk ? 100 ? s
fedl7074-003-01 ML7074-004 7/98 electrical characteristics dc characteristics (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditions min. typ. max. unit iss standby state (pdnb = ?0?, v dd = 3.3 v, ta = 25 ? c) ? 5.0 20.0 ? a i dd 1 operating state 1 in the pcm/if mode (sc_en = ?1?, pcmif_en = ?1?, afe_en = ?1?) connect a 4.096 mhz crystal oscillator between xi and xo. ? 45.0 55.0 ma power supply current i dd 2 operating state 2 when operating the whole system (sc_en = ?1?, pcmif_en = ?0?, afe_en = ?0?) connect a 4.096 mhz crystal oscillator between xi and xo. ? 50.0 65.0 ma iih vin = dv dd ? 0.01 1.0 ? a digital input pin input leakage current iil vin = dgnd ? 1.0 ? 0.01 ? ? a iozh vout = dv dd ? 0.01 1.0 ? a digital i/o pin output leakage current iozl vout = dgnd ? 1.0 ? 0.01 ? ? a high level output voltage voh digital output pins, i/o pins ioh = 4.0 ma ioh = 1.0 ma (xo pin) 2.2 ? ? v low level output voltage vol digital output pins, i/o pins iol = ? 4.0 ma iol = ? 1.0 ma (xo pin) ? ? 0.4 v input capacitance *1 cin input pins ? 8 12 pf note: *1 guaranteed design value
fedl7074-003-01 ML7074-004 8/98 analog interface (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditions min. typ. max. unit input resistance *1 rin ain0n, ain0p, ain1n 10 ? ? m ? output load resistance rl gs x0, gsx1, vfro0, vfro1 10 ? ? k ? output load capacitance cl analog output pins ? ? 50 pf offset voltage vof vfro0, vfro1 ? 40 ? 40 mv output voltage level *2 vo gsx0, gsx1, vfro0, vfro1 rl = 10 k ? ? ? 1.3 vpp notes: *1 guaranteed design value *2 ? 7.7 dbm (600 ? ) = 0 dbm0, +3.17 dbm0 = 1.3 vpp
fedl7074-003-01 ML7074-004 9/98 ac characteristics codec (speech codec in g.711 ( ? -law) mode) (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) conditions parameter symbol frequency (hz) level (dbm0) min. typ. max. unit lt1 0 to 60 25 ? ? db lt2 300 to 3000 ? 0.15 ? 0.20 db lt3 1020 reference value ? lt4 3300 ? 0.15 ? 0.80 db lt5 3400 0 ? 0.80 db transmit frequency characteristics lt6 3968.75 0 13 ? ? db lr2 0 to 3000 ? 0.15 ? 0.20 db lr3 1020 reference value ? lr4 3300 ? 0.15 ? 0.80 db lr5 3400 0 ? 0.80 db receive frequency characteristics lr6 3968.75 0 13 ? ? db sdt1 3 35 ? ? dbp sdt2 0 35 ? ? dbp sdt3 ? 30 35 ? ? dbp sdt4 ? 40 28 ? ? dbp transmit signal to noise ratio [*1] sdt5 1020 ? 45 23 ? ? dbp sdr1 3 35 ? ? dbp sdr2 0 35 ? ? dbp sdr3 ? 30 35 ? ? dbp sdr4 ? 40 28 ? ? dbp receive signal to noise ratio [*1] sdr5 1020 ? 45 23 ? ? dbp gtt1 3 ? 0.2 ? 0.2 db gtt2 ? 10 reference value ? gtt3 ? 40 ? 0.2 ? 0.2 db gtt4 ? 50 ? 0.6 ? 0.6 db transmit inter-level loss error gtt5 1020 ? 55 ? 1.2 ? 1.2 db gtr1 3 ? 0.2 ? 0.2 db gtr2 ? 10 reference value ? gtr3 ? 40 ? 0.2 ? 0.2 db gtr4 ? 50 ? 0.6 ? 0.6 db receive inter-level loss error gtr5 1020 ? 55 ? 1.2 ? 1.2 db nidlt ? analog input = avref ? ? ? 68 dbm0p idle channel noise [*1] nidlr ? pcmi = ?1? ? ? ? 72 dbm0p transmit absolute level [*2] avt 1020 0 0.285 0.320 0.359 vrms receive absolute level [*2] avr 1020 0 0.285 0.320 0.359 vrms psrrt ? 30 ? ? db power supply noise reject ratio psrrr noise frequency range: 0 to 50 khz noise level: 50mvpp ? 30 ? ? db notes: *1 using p-message filter *2 0.320 vrms = 0 dbm0 = ? 7.7 dbm (600 ? )
fedl7074-003-01 ML7074-004 10/98 gain setting (speech codec in g.711 ( ? -law) mode) (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit transmit and receive gain setting accuracy gac ? ? 1.0 ? 1.0 db tone output (speech codec in g.711 ( ? -law) mode) (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit frequency deviation fdft relative to set frequency ? 1.5 ? 1.5 % output level olev relative to set gain ? 2.0 ? 2.0 db dtmf detector, other detector s (speech codec in g.711 ( ? -law) mode) (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit detect level accuracy dlac relative to set detect level ? 2.5 ? 2.5 db echo canceller (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit in the analog i/f mode in the pcm i/f (16-bit linear) mode 35 echo attenuation eres in the pcm i/f (g.711) mode ? 30 ? db erasable echo delay time tect ? ? ? 32 ms measurement method sin sout delay white noise generator rout rin att e.r.l (echo return loss) echo delay time echo canceller lpf 5 khz level meter
fedl7074-003-01 ML7074-004 11/98 pdnb, xo, avref timings (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit power down signal pulse width tpdnb pdnb pin 1 ? ? ? s oscillation start-up time txtal ? ? 2+ ? 100 ms avref rise time tavref avref = 1.4 (90%) c5 = 4.7 ? f, c6 = 0.1 ? f (see fig. 9.) ? ? 600 ms initialization mode start-up time tinit ? ? 1 ? s * ?? is a value that depends on the oscillation stab ilizing time when using a crystal oscillator. fig. 1 pdnb, xo, and avref timings pdnb avref about 1.4 v 0 v vdd xo 0 v vdd txtal 0 v t avref dvdd, avdd 0 v vdd t pdnb "1" "0" cr5-b7 (ready) initialization mode t init
fedl7074-003-01 ML7074-004 12/98 pcm i/f mode (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit bit clock frequency fbclk cdl = 20pf(at output) ? 0.1% 64 +0.1% khz bit clock duty ratio dbclk cdl = 20pf(at output) 45 50 55 % sync signal frequency fsync cdl = 20pf(at output) ? 0.1% 8 +0.1% khz dsync1 cdl = 20pf(at output) at 64 khz output 12.4 12.5 12.6 % sync signal duty ratio dsync2 cdl = 20pf(at output) at 128 khz output 6.24 6.25 6.26 % tbs bclk to sync (at output) 100 ? ? ns transmit/receive signal sync timing tsb sync to bclk (at output) 100 ? ? ns input setup time tds ? 100 ? ? ns input hold time tdh ? 100 ? ? ns tsdx ? ? 100 ns digital output delay time txd1 ? ? 100 ns txd2 ? ? 100 ns digital output hold time txd3 pcmo pin pull-up, pull-down resistors rdl = 1 k ? , cdl = 50 pf ? ? 100 ns 01 msb lsb tws tds tdh bclk sync pcmi tbs tsb 2 3 4 5 6 7 8 - 16 g.711 lsb 16bit linear fig. 2 pcm i/f mode input timing (long frame) 01 tws tds tdh bclk sync pcmi tbs tsb 2 3 4 5 6 7 8 9 - msb lsb g.711 17 lsb 16bit linear fig. 3 pcm i/f mode input timing (short frame)
fedl7074-003-01 ML7074-004 13/98 01 lsb tws bclk sync pcmo tbs tsb 2 3 4 5 6 7 8 9 - msb hi-z tsdx txd1 txd2 txd3 g.711 17 lsb txd3 16bit linear fig. 4 pcm i/f mode output timing (long frame) 01 lsb tws bclk sync pcmo tbs tsb 2 3 4 5 6 7 8 9 10 msb hi-z txd1 txd2 txd3 g.711 - 18 lsb 16bit linear txd3 fig. 5 pcm i/f mode out put timing (short frame)
fedl7074-003-01 ML7074-004 14/98 control register interface (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit address setup time tas 10 ? ? ns address hold time tah 10 ? ? ns write data setup time twds 10 ? ? ns write data hold time twdh 10 ? ? ns csb setup time tcs 10 ? ? ns csb hold time tch 10 ? ? ns wrb pulse width tww 10 ? ? ns read data output delay time trdd ? ? 20 ns read data output hold time trdh 3 ? ? ns rdb pulse width trw 25 ? ? ns csb disable time tcd cl = 50 pf 10 ? ? ns fig. 6 control register interface a7-a0 input d7-d0 i/o csb input wrb input rdb input write timing read timing tas tah twds twdh tch trdd tcs trdh tww trw a1 d1 input a2 d2 output tcs tch tas tah tcd
fedl7074-003-01 ML7074-004 15/98 transmit and receive buffer interface (in frame mode) (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit fr1b setup time tf1s 3 ? ? ns fr1b output delay time tf1d ? ? 20 ns address setup time tas 10 ? ? ns address hold time tah 10 ? ? ns write data setup time twds 10 ? ? ns write data hold time twdh 10 ? ? ns csb setup time tcs 10 ? ? ns csb hold time tch 10 ? ? ns wrb pulse width tww 10 ? ? ns fr0b setup time tf0s 3 ? ? ns fr0b output delay time tf0d ? ? 20 ns read data output delay time trdd ? ? 30 ns read data output hold time trdh 3 ? ? ns rdb pulse width trw 35 ? ? ns csb disable time tcd cl = 50 pf 10 ? ? ns fig. 7 transmit and receive buffer interface (in frame mode) a7-a0 input d15-d0 i/o csb input wrb input rdb input write timing read timing tas tah twds twdh tch trdd tcs trdh tww trw a1 d1 input a2 d2 output tcs tch tas tah fr1b output fr0b output tf1s tf1d tf0s tf0d tcd a7-a0 input d15-d0 i/o csb input wrb input rdb input write timing read timing tas tah twds twdh tch trdd tcs trdh tww trw a1 d1 input a2 d2 output tcs tch tas tah fr1b output fr0b output tf1s tf1d tf0s tf0d tcd
fedl7074-003-01 ML7074-004 16/98 transmit and receive buffer interface (in dma mode) (unless otherwise specified, av dd = 3.0 to 3.6 v, dv dd 0, 1, 2 = 3.0 to 3.6 v, ag nd = dgnd0, 1, 2 = 0.0 v, ta = ? 20 to +60 ? c) parameter symbol conditio ns min. typ. max. unit dmarq1b setup time tdr1s 3 ? ? ns tdr1rd ? ? 25 ns dmarq1b output delay time tdr1fd ? ? 25 ns address setup time tas 10 ? ? ns address hold time tah 10 ? ? ns write data setup time twds 10 ? ? ns write data hold time twdh 10 ? ? ns ack setup time taks 10 ? ? ns ack hold time takh 10 ? ? ns wrb pulse width tww 10 ? ? ns dmarq0b setup time tdr0s 3 ? ? ns tdr0rd ? ? 20 ns dmarq0b output delay time tdr0fd ? ? 25 ns read data output delay time trdd ? ? 30 ns read data output hold time trdh 3 ? ? ns rdb pulse width trw 35 ? ? ns ackb disable time tad cl = 50 pf 10 ? ? ns fig. 8 transmit and receive buffer interface (in dma mode) a7-a0 input d15-d0 i/o ack0b input wrb input rdb input write timing read timing tas tah twds twdh trdd taks trdh tww trw a1 d1 input a2 d2 output takh tas tah dmarq1b output dmarq0b output tdr1s tdr1rd tdr0s tdr0rd ack1b input takh taks tad tdr1fd tdr0fd
fedl7074-003-01 ML7074-004 17/98 pin function descriptions ain0n, ain0p, gsx0, ain1n, gsx1 these are the analog transmit input and transmit level adjust pins. each of ain0n and ain1n is connected to each of the inverting input pins of the built-in transmit amp lifiers amp0 and amp1, and ain0p is connected to the non-inverting input pin of amp0. in addition, gsx0 and gsx1 are connected to the output pins of amp0 and amp1, respectively. the selection between amp0 and amp1 is made by cr10-b0. see fig. 9 for the method of making level adjustment. during the power down mode (when pdnb = ?0? or cr0-b7 = ?1?), the outputs of gsx0 and gsx1 go to the high impedance state. if amp0 is not used in the specific application of this lsi, short gsx0 with ain0n and connect ain0p with avref. when amp1 is not used, short gsx1 with ain1n. notice: it is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise will be generated if the amplifier selection is changed while conversation is in progress. vfro0, vfro1 these are analog receive output pins and are connected to th e output pins of the built-in receive amplifiers amp2 and amp3, respectively. the output signals of vfro0 and vfro1 can be selected using cr10-b1 and cr10-b2, respectively. when selected (?1?), the received signal will be output, and when deselected (?0?), the avref signal (about 1.4 v) will be output. in the power down mode , these pins will be in the high impedance state. it is recommended to use these output signals via dc coupling capacitors. notice: it is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise is generated if the output selection is changed while the conversation is in progress. at the time of resetting or releasing from the reset stat e, it is recommended to select the avref as outputs of vfro0 and vfro1. fig. 9 analog interface r1 r2 a/d d/a vref ain1n gsx1 avref ???? ain0n gsx0 10k ? ain0p r3 r4 c6 0.1 ? f c1 c2 c3 c4 vfro0 10k ? vfro1 10k ? c5 2.2 to 4.7 ? f cr10-b0 cr10-b1 cr10-b2 gain = r2/r1 <= 63(+36db) r1 : variable r2 : max 500k + gain = r4/r3 <=63(+36db) r3 : variable r4 : max 500k out : max 1.3vp-p out : max 1.3vp-p amp0 amp1 amp3 amp2
fedl7074-003-01 ML7074-004 18/98 avref this is the output pin for the analog signal ground potential. the output potential at this pin will be about 1.4 v. connect a 2.2 to 4.7 ? f (aluminum electrolytic type) capacitor and a 0.1 ? f (ceramic type) capacitor in parallel between this pin and the gnd pin as bypass capacitors. the output at the avref pin goes to 0.0 v in the power down mode. the voltage starts rising after the power down mode is released (pdnb = ?1? and also cr0-b7 = ?0?). the rise time is about 0.6 seconds. xi, xo these are the pins for either connecting the crystal oscillator for the master clock or for inputting an external master clock signal. the oscillations of the master clock oscillator will be stopped during a power down due to the pdnb signal or during a software power down due to cr0-b7 (spdn). the oscillations start when the power down condition is released, and the internal clock supply of the lsi will be started after counting up the oscillation stabilization period (of about 16 ms). examples of crystal oscillato r connection and external master clock input are shown in fig. 10. fig. 10 examples of oscilla tor circuit and clock input pdnb this is the power down control input pin. the power down m ode is entered when this pin goes to ?0?. in addition, this pin also has the function of resetting the lsi. in order to prevent wrong operation of the lsi, carry out the initial power-down reset after switching on the power using this pdnb pin. also, keep the pdnb pin at ?0? level for 1 ? s or more to initiate the power down state. further, it is possible to carry out a power down reset of the lsi when the power is being supplied by performing control of cr0-b7 (spdn) in the sequence ?0? ? ?1? ? ?0?. the ready signal (cr5-b7) goes to ?1? about 1.0 second afte r the power down mode is released thereby entering the mode of setting various functions (initialization mode). see fig. 1 for the timings of pdnb and avref, xo, and the initialization mode. notice: at the time of switching on the power, start from the power down mode using pdnb. dv dd 0, dv dd 1, dv dd 2, av dd these are power supply pins. dv dd 0, 1, 2 are the power supply pins for the digital circuits while av dd is the power supply pin for the analog circuits of the lsi. connect these pins together in the neighborhood of the lsi and connect as bypass capacitors a 10 ? f electrolytic capacitor and a 0.1 ? f ceramic capacitor in parallel between the dgnd and agnd pins. dgnd0, dgnd1, dgnd2, agnd these are ground pins. gdnd0, 1, 2 are the ground pins for the digital circuits and agnd is the ground pin for the analog circuits of the lsi. connect these pi ns together in the neighborhood of the lsi. xi xo r x'tal c1 c2 4.096 mhz x'tal(4.096 mhz) daishinku co., ltd. at-49 c2 r 10pf 1m ? pdnb to internal circuits cr0-b7 (spdn) xi xo open pdnb to internal circuits cr0-b7 (spdn) c1 5pf
fedl7074-003-01 ML7074-004 19/98 tst0, tst1, tst2, tst3 these are input pins for testing purposes only. keep the inputs to these pins at the ?0? level during normal use conditions. intb this is the interrupt request output pin. an ?l? level is output for a duration of about 1.0 ? s at this pin when there is a change in state of an interrupt cause. this output will be maintained at the ?h? level when there is no change in state of any of the interrupt causes. the actual interrupt cause generating the interrupt can be verified by reading cr3, cr4, and cr5. the different interrupt causes are described below. ? underflow error (cr3-b0) an interrupt is generated when an internal read from th e receive buffer occurs before the writing into the receive buffer from the mcu has been completed. an interrupt is generated when a normal writing is ma de in the receive buffer by the mcu and the underflow error is released. ? overrun error (cr3-b1) an interrupt is generated when an internal write of th e next data into the transmit buffer occurs before the transmit buffer data read out from the mcu has been completed. an interrupt is generated when a normal read out is made from the transmit buffer by the mcu and the overrun error is released. ? when a dial pulse is detected (cr4-b6). ? when a dtmf signal is detected (cr4-b4). ? when dtmf_codec0, 1, 2, 3 are detected (cr4-b0, b1, b2, b3). an interrupt is generated when a dtmf signal is detected. an interrupt is generated when there is a change from the dtmf signal det ected state to the no-detected state. an interrupt is generated when there is a change in th e detected code (cr4-b0, b1 , b2, b3) in the condition in which a dtmf signal is being detected. ? when tone0 is detected (cr3-b3). an interrupt is generated when a 1650 hz tone signal is detected. an interrupt is generated when there is a change to the non-detection condition in the tone signal detection condition. ? when tone1 is detected (cr3-b4). an interrupt is generated when a 2100 hz tone signal is detected. an interrupt is generated when there is a change to the non-detection condition in the tone signal detection condition. ? when dsp_err is detected (cr3-b7). an interrupt is generated when any error occurs in the dsp inside the lsi. ? when fgen_flag is cleared (cr5-b0). fgen_flag is cleared to ?0? and an interrupt is generated when data settings are enabled to output data setting register fgen_d[7:0] (cr18) in the fsk generator.
fedl7074-003-01 ML7074-004 20/98 a0 to a7 these are the address input pins for us e during an access of the frame, dma, or control registers. the different addresses will be the following. transmit buffer (tx buffer) a7 to a0 = 10xxxxxxb (the lower 6 bits are not valid) receive buffer (rx buffer) a7 to a0 = 01xxxxxxb (the lower 6 bits are not valid) control register (cr) a7 to a0 = 00xxxxxxb d0 to d15 these are the data input/output pins for use during an access of the frame, dma, or control registers. connect pull-up resistors to these pins since they are i/o pins. when the 8-bit bus access method is selected by cr11-b5, only d0 to d7 become valid. since the higher 8 bits d8 to d15 will always be in the input state when the 8-bit bus access method is selected (cr11-b5 = ?1 ?), tie them to ?0? or ?1? inputs. csb this is the chip select input pin for use during a frame or control register access. rdb this is the read enable input pin for use du ring a frame, dma, or control register access. wrb this is the write enable input pin for use du ring a frame, dma, or control register access.
fedl7074-003-01 ML7074-004 21/98 fr0b (dmarq0b) ? fr0b (in frame mode, cr11-b7 = ?0?) this is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame access. this pin outputs an ?l? level when the transmit buffer becomes full, and maintains that ?l? level output until a specific number of words are read out from the mcu. ? dmarq0b (in dma mode, cr11-b7 = ?1?) this is the dma request output pin which outputs the si gnal when the transmit buffer is full during dma access. this output becomes ?l? when the transmit buffer become s full, and returns to the ?h? level automatically on the falling edge of the read enable signal (rdb = ?1? ? ?0?) when there is an ac knowledgement signal (ack0b = ?0?) from the mcu. this relationship is repeated un til a specific number of words are read out from the mcu. fr1b (dmarq1b) ? fr1b (in frame mode, cr11-b7 = ?0?) this is the receive frame output pin which outputs the signal when the receive bu ffer is empty during frame access. this pin outputs an ?l? level when the receive buffer becomes empty, and maintains that ?l? level output until a specific number of words are written from the mcu. ? dmarq1b (in dma mode, cr11-b7 = ?1?) this is the dma request output pin which outputs th e signal when the receive buffer is empty during dma access. this output becomes ?l? when the receive buf fer becomes empty, and returns to the ?h? level automatically on the falling edge of the write enable signal (wrb = ?1? ? ?0?) when there is an acknowledgement signal (ack1b = ?0?) fr om the mcu. this relationship is repeated until a specific number of words are written from the mcu. ack0b this is the dma acknowledgement input pin for the dm arq0b signal during dma ac cess of the transmit buffer and becomes valid in the dma mode (cr11-b7 = ?1?). tie this pin to ?1? when using this lsi in the frame access mode (cr11-b7 = ?0?). ack1b this is the dma acknowledgement input pin for the dm arq1b signal during dma access of the receive buffer and becomes valid in the dma mode (cr11-b7 = ?1?). tie this pin to ?1? when using this lsi in the frame access mode (cr11-b7 = ?0?). gpi0, gpi1 these are general-purpose input pins. the state (?1? or ?0?) of each of these gpi0 and gpi1 pins can be read out respectively from cr16-b0 and cr16-b1. further, gpi0 becomes the input pin for the dial pulse detector (dpdet) in the secondary functions. gpo0, gpo1 these are general-purpose output pins. the values set in cr17-b0 and cr17-b1 are output at these pins gpo0 and gpo1, respectively. further, gpo0 becomes the output pin for the dial pulse generator (dpgen) in the secondary functions.
fedl7074-003-01 ML7074-004 22/98 clksel this is the input/output control input pin of sync and bclk. the pin becomes input at ?0? level and output at ?1? level. sync this is the 8 khz sync signal input/output pin of pcm signals. when clksel is ?0?, input continuously an 8 khz clock synchronous with bclk. further, when clksel is ?1?, this pin outputs an 8 khz clock synchronous with bclk. long frame synchronization is used wh en cr0-b1 (long/short) is ?0? and short frame synchronization is used when it is ?1?. bclk this is the shift clock input/output pin for the pcm signal. when clksel is ?0?, it is necessary to input to this pin a clock signal that is synchronous with sync. input a 64 to 2048 khz clock when the g.711 mode has been selected, and input a 128 to 2048 khz clock when the 16-bit linear mode has been selected. when clksel is ?1?, this pin outputs a clock that is synchronous with sync. this pin outputs a 64 khz clock when the g.711 mode has been selected, and outputs an 128 khz clock when the 16-bit linear mode or g.729.a mode has been selected. note: the input/output control and frequencies of the a bove sync and blck signals will be as shown in table 1 below. table 1 input/output control of sync and bclk clksel sync bclk remarks ?0? input (8 khz) input (64 khz to 2048 khz) input a continuous clock after starting the power supply. input a 64 to 2048 khz clock when g.711 is selected. input a 128 to 2048 khz clock when 16-bit linear mode is selected. ?1? output (8 khz) output (64 khz or 128 khz) an ?l? level is output during the power down mode. a 64 khz clock is output when g.711 is selected. a 128 khz clock is output when g.729.a or 16-bit linear mode is selected. pcmo this is the pcm signal output pin for the transmitting section. the pcm signal is output in synchronization with the rising edges of sync and bclk. the pcmo outputs the data only during the valid data segment in the selected coding format and goes to th e high impedance state during all othe r segments. the basic timing chart of the pcm i/f mode is shown in fig. 11. the pcmo output will be in the high impedance state when the pcm i/f mode is not used (cr12-b0 = ?0?). pcmi this is the pcm signal input pin for the receiving section. the data is entered starting from the msb by shift on the falling edge of bclk. the basic timing chart of the pcm i/f mode is shown in fig. 11. fix input to ?0? or ?1? when the pcm i/f mode (cr12-b0 = ?0?) is not used.
fedl7074-003-01 ML7074-004 23/98 fig. 11 pcm i/f mode timing diagram bclk (in/out)) pcmi sync (in/out) - 16-bit linear - long frame synchronization mode (cr0-b1="0") d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 bclk (in/out) pcmo sync (in/out)) - g.711( ? -law,a-law) - short frame synchronization mode(cr0-b1="1") d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z pcmo d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z pcmi d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 bclk (in/out)) pcmi sync (in/out) d15 d14 d13 d12 d11 d10 d9 d8 bclk (in/out) pcmo sync (in/out)) - 16-bit linear - short frame synchronization mode (cr0-b1="1") hi-z pcmo hi-z hi-z pcmi d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d7 d6 d5 d15 d14 d13 d12 d11 d10 d9 d8 ? ? d15 d14 d13 d12 d11 d10 d9 d8 hi-z d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d7 d6 d15 d14 d13 d12 d11 d10 d9 d8 ? ? - g.711( ? -law,a-law) - long frame synchronization mode (cr0-b1="0")
fedl7074-003-01 ML7074-004 24/98 function description on the transmit and receive buffers the controllable parameters of the transmit an d receive buffers are shown in table 2 below. table 2 controllable parameters of transmit and receive buffers content changeable parameter initial value remarks speech codec g.729.a/g.711( ? -law, a-law) g.729.a the buffering size of the fifo is changed automatically depending on the speech codec type. buffering time 10 ms/20 ms 10 ms the number of words is changed automatically depending on the buffering time. accessing method frame or dma frame ? fifo data width 16-bit/8-bit 16-bit the number of words is changed automatically depending on the data width. transmit and receive buffer sizes the transmit and receive buffers have a double buffer configuration of the fifo (first in first out) type, and one buffer can buffer data of 10 ms or 20 ms. the timing of generation of the frame signals (fr0b, fr1b) requested to the mcu when the transmit buffer is full or the receive buffer is empty, an d the timing of generation of the dma request signals (dmarq0b, dmarq1b) depend on the buffering time. further, the number of words of fifo is changed automatically depending on the selected speech codec type and the fifo data width. the buffer size and the number of words for the different speech codec types and data widths are shown in table 3. table 3 buffer size and number of words of transmit and receive buffers 10 ms mode 20 ms mode speech codec buffer size 16-bit 8-bit buffer size 16-bit 8-bit g.729.a (8 kbps) 10 bytes 5 words 10 words 20 bytes 10 words 20 words g.711 (64 kbps) 80 bytes 40 words 80 words 160 bytes 80 words 160 words
fedl7074-003-01 ML7074-004 25/98 transmit and receive buffers configuration the timings of accessing the transmit and receive buffers are shown in fig. 12. although bot h transmit and receive buffers have a double buffer configuration, they can be accessed as a single buffer from the mcu. fig. 12 timings of accessing the transmit and receive buffers transmit buffer tx buffer0 10 m/20 msec receive buffer rx buffer0 writing in from mcu reading out from mcu tx buffer1 tx buffer0 rx buffer1 rx buffer0
fedl7074-003-01 ML7074-004 26/98 data width selection (16-bit mode, 8-bit mode) in the method of accessing the transmit a nd receive buffers, it is possible to sel ect data width of 16 bits or 8 bits using the control register bit cr11-b5. during the 16-bit mode, the access is made with a data width of 16 bits and the data bits d15 to d0 are accessed. in the 8-bit mode, the transmit and receive da ta are input or output to d7 to d0. during the 8-bit access mode, the bits d15 to d8 will always be in the input state. data storage format the data storage formats during transmission and reception depending on the settings of the different parameters are shown in fig. 13 and fig. 14. a. g.729.a fig. 13 g.729.a data format g.729.a(8 kbps) 1 frame 80-bit/10 ms 2 frames 160-bit/20 ms bit15 bit0 bit31 bit16 bit63 bit48 bit79 bit64 (a) 10 ms/16-bit mode (b) 20 ms/16-bit mode first frame bit7 bit0 (c) 10 ms/8-bit mode first frame bit15 bit8 bit71 bit64 bit79 bit72 (d) 20 ms/8-bit mode d15 d0 d15 d0 d7 d0 d7 d0 word count 1 2 4 5 bit47 bit32 3 word count 1 2 9 10 bit7 bit0 bit15 bit8 bit71 bit64 bit79 bit72 bit7 bit0 bit15 bit8 bit71 bit64 bit79 bit72 bit15 bit0 bit31 bit16 bit63 bit48 bit79 bit64 bit47 bit32 bit15 bit0 bit31 bit16 bit63 bit48 bit79 bit64 bit47 bit32 first frame second frame word count 1 2 9 10 11 12 19 20 first frame word count 1 2 4 5 3 6 7 9 10 8 second frame gb2 0 gb2 1 gb2 2 gb2 3 ga2 0 ga2 1 ga2 2 s2 0 s2 1 s2 2 s2 3 c2 0 c2 1 c2 2 c2 3 c2 4 c2 5 c2 6 c2 7 c2 8 c2 9 c2 10 c2 11 c2 12 p2 0 p2 1 p2 2 p2 3 p2 4 gb1 0 gb1 1 gb1 2 gb1 3 ga1 0 ga1 1 ga1 2 s1 0 s1 1 s1 2 s1 3 c1 0 c1 1 c1 2 c1 3 c1 4 c1 5 c1 6 c1 7 c1 8 c1 9 c1 10 c1 11 c1 12 p0 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 l3 0 l3 1 l3 2 l3 3 l3 4 l2 0 l2 1 l2 2 l2 3 l2 4 l0 word count 1 2 4 5 3 l1 0 l1 1 l1 2 l1 3 l1 4 l1 5 l1 6 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 g.729.a coding, word configuration word configuration symbol name bit no.
fedl7074-003-01 ML7074-004 27/98 b. g.711 (64 kbps) fig. 14 g.711 data format g.711(64 kbps, ? -law/a-law) 8 bit/125 ? s buffer configuration 80 samples/10 ms 160 samples/20 ms (a) 10 ms/16-bit mode (b) 20 ms/16-bit mode bit7 bit6 bit5 bit4 pcm coding configuration bit3 bit2 bit1 bit0 1 0 3 157 156 159 158 0 (c) 10 ms/8-bit mode 78 79 (d) 20 ms/16-bit mode word configuration 1 2 39 40 . . 1 2 79 80 . . 1 2 79 80 . . 0 158 159 1 2 159 160 . . word count word count word count word count 1 0 3 77 76 79 78 bit7 bit0 bit7 bit0 2 2 bit7 bit0 2 1 1 bit7 bit0 d15 d0 d7 d0 d15 d0 d7 d0
fedl7074-003-01 ML7074-004 28/98 transmit and receive buffer control method the methods of controlling the tran smit and receive buffers dependin g on the different parameters are shown in figs. 15 to 18. a. g.729.a ( 10 ms/frame mode ) fig. 15 g.729.a control timing (10 ms/frame mode) fr0b (output) read out by mcu read out valid segment 4) error tx_err (cr3-b1) 10 ms enc speech codec init t1 t2 t3 t4 t5 t8 t6 t7 stoppde t9 sc_en (cr2-b7) 1) start maximum 250 ? s 2) operating 3) stop maximum 250 ? s 5) start interval 10.0 ms or more stopped re1 re2 re3 re4 re5 re6 re7 re8 init about 125 ?? s 10 ms speech codec no-tone output dec out no-tone output/init no-tone output/init fr1b (output) write in by mcu write valid segment we1 intb (output) rx_err (cr3-b0) dec_outon (cr2-b5) we2 we3 we4 we5 we6 we7 we8 we 9 we10 t wait about 15 ms r5 r6 r7 r8 r1 r2 r3 r4 (bfi) no-tone output no- tone about125 ? s 4) error 10 ms 1) start dec_outon ?0?, sc_en ?0? ? ?1? the speech codec starts within about 250 ? s after sc_en has been set to ?1?. the encoder is initialized during the first 10 ms period, and starts encoding with the t1 se gment. the decoder carries out initialization after the speech codec has been started, and outputs no-tone data. if the first receive data has been written and the twait wait time has elapsed, the dec output control bit (dec_outon) can be set to ?1?. (twait = 1 ms or more) the decoder starts decoder output about 15 ms after dec_outon is set to ?1?. 2) operating the data encoded during encode segment tn is read by the mcu during read valid segment ren. this operation is repeated until the speech codec is stopped. (n = 1, 2, 3, 4, ?) the data written by the mcu during write valid segment wen is output during decoder output segment rn. this operation is repea ted until the speech codec is stopped. (n = 1, 2, 3, 4, ?) 3) stop set sc_en ?1? ? ?0?, dec_outon ?1? ? ?0? encoding and decoding after the stoppage of the speech codec is disabled. within about 250 ? s after sc_en has been set to ?1?, the encoder stops writing data, and the decoder stops and then outputs no-tone data. 4) error processing receive error: in the figure above, an example of a receive error occurrence is shown in the write valid segment we4. if data writing is not completed within a write valid segment, rx_err is set to ?1? and an interrupt is generated. the state o f rx_err will be maintained during and after the next write valid segment until just before the end of a frame that has been written normally into the rx buffer. if an error occurs in the write valid segment we4, the loss-of-frame compensation processing (bfi: bad frame indicator) specif ied in g.729a will be performed. transmit error: in the figure above, an example of a transmit error occurrence is shown in the read valid segment re5. if data reading is not completed within a read valid segment, tx_err is set to ?1? and an interrupt is generated. the state of tx_err will be maintained during and after the next read valid segment until just before the end of a frame that has been read normally from the transmit buffer. even if data reading is not completed, the data in the transmit buffer is updated as usual. 5) start interval an interval of 10.0 ms or more is required after the speech codec has stopped before it is started again. during this interval , it is possible to change the speech codec. write valid segment: there is no restriction of time on the first write valid segment (we1) after the speech codec is started. for the write valid segment we2 and after, complete the writing of data to the rx buffer within 9.0 ms from the falling edge o f fr1b. read valid segment: complete the reading of data from the tx buffer within 9.0 ms from the falling edge of fr0b.
fedl7074-003-01 ML7074-004 29/98 fig. 16 g.729.a control timing (20 ms/frame mode) b. g.729.a (20 ms/frame mode) fr0b (output) read out by mcu read out valid segment 4) error tx_err (cr3-b1) 20 ms enc speech codec init t1 t3 t5 t7 stopped t9 sc_en (cr2-b7) 1) start maximum 250 ? s 2) operating 3) stop maximum 250 ? s 5) start interval 10.0 ms or more stopped re1 re3 re5 re7 init fr1b (output) write in by mcu write valid segment intb (output) rx_err (cr3-b0) we1 dec_outon (cr2-b5) about 125 ? s about 10 ms 20 ms speech codec no-tone output dec out no-tone output/init 20 ms about 15 ms 4) error we3 we5 we7 we9 we11 about 125 ? s t wait r5(bfi) r7 r1 r3 no-tone output no-tone output/init no-tone 1) start dec_outon ?0?, sc_en ?0? ? ?1? the speech codec starts within about 250 ? s after sc_en has been set to ?1?. the encoder is initialized during the first 10 ms period, and starts encoding with the t1 segment. the decoder carries out initialization after the speech codec has been started, and outputs no-tone data. if the first receive data has been written and the twait wait time has elapsed, the dec output control bit (dec_outon) can be set to ?1?. (twait = 1 ms or more) the decoder starts decoder output about 15 ms after dec_outon is set to ?1?. 2) operating the data encoded during encode segment tn is read by the mcu during read valid segment ren. this operation is repeated until the speech codec is stopped. (n = 1, 2, 3, 4, ?) the data written by the mcu during write valid segment wen is output during decoder output segment rn. this operation is repea ted until the speech codec is stopped. (n = 1, 2, 3, 4, ?) 3) stop set sc_en ?1? ? ?0?, dec_outon ?1? ? ?0? encoding and decoding after the stoppage of the speech codec is disabled. within about 250 ? s after sc_en has been set to ?1?, the encoder stops writing data, and the decoder stops and then outputs no-tone data. 4) error processing receive error: in the figure above, an example of a receive error occurrence is shown in the write valid segment we5. if data writing is not completed within a write valid segment, rx_err is set to ?1? and an interrupt is generated. the state o f rx_err will be maintained during and after the next write valid segment until just before the end of a frame that has been written normally into the rx buffer. if an error occurs in the write valid segment we5, the loss-of-frame compensation processing (bfi: bad frame indicator) specif ied in g.729a will be performed. transmit error: in the figure above, an example of a transmit error occurrence is shown in the read valid segment re5. if data reading is not completed within a read valid segment, tx_err is set to ?1? and an interrupt is generated. the state of tx_err will be maintained during and after the next read valid segment until just before the end of a frame that has been read normally from the transmit buffer. even if data reading is not completed, the data in the transmit buffer is updated as usual. 5) start interval an interval of 10.0 ms or more is required after the speech codec has stopped before it is started again. during this interval , it is possible to change the speech codec. write valid segment: there is no restriction of time on the first write valid segment (we1) after the speech codec is started. for the write valid segment we3 and after, complete the writing of data to the rx buffer within 18.0 ms from the falling edge of fr1b. read valid segment: complete the reading of data from the tx buffer within 18.0 ms from the falling edge of fr0b.
fedl7074-003-01 ML7074-004 30/98 c. g.711 ( ? -law, a-law) (10 ms/frame mode) fig. 17 g.711 ( ? -law, a-law) control timing (10 ms/frame mode) fr0b (output) read out by mcu read out valid segment 4) error tx_err (cr3-b1) 10 ms enc speech codec t1 t2 t3 t4 t5 t6 t9 t7 t8 stopped/init t1 t10 sc_en (cr2-b7) 1) start maximum 250 ? s 2) operating 3) stop maximum 250 ? s 5) start interval 10.0 ms or more stopped/init re1 re2 re3 re4 re5 re6 re7 re8 re9 fr1b (output) write in by mcu write valid segment intb (output) rx_err (cr3-b0) we1 speech codec dec_outon (cr2-b5) t wait about 125 ? s stopped output/init r5 r6 r7 r8 r9 r1 r2 r3 r4 (plc) no-tone output/init dec out no- tone 10 ms about 3.75 ms 10 ms we2 4) error we3 we4 we5 we6 we7 we8 we9 we10 about 125 ? s we11 1) start dec_outon ?0?, sc_en ?0? ? ?1? the speech codec starts within about 250 ? s after sc_en has been set to ?1?. the encoder starts in the already initialized condition and starts encoding immediately aft er the speech codec has been started. the decoder carries out initialization after the speech codec has been started, and outputs no-tone data. if the first receive data has been written and the twait wait time has elapsed, the dec output control bit (dec_outon) can be set to ?1?. (twait = 1 ms or more) after setting dec_outon to ?1?, the decoder outputs no-tone data for about 3.75 ms, and then starts decoder output. however, if the plc function has been disabled, the decoder starts decoder output after setting dec_out_on to ?1?. 2) operating the data encoded during encode segment tn is read by the mcu during read valid segment ren. this operation is repeated until the speech codec is stopped. (n = 1, 2, 3, 4, ?) the data written by the mcu during write valid segment wen is output during decoder output segment rn. this operation is repea ted until the speech codec is stopped. (n = 1, 2, 3, 4, ?) 3) stop set sc_en ?1? ? ?0?, dec_outon ?1? ? ?0? encoding and decoding after the stoppage of the speech codec is disabled. within about 250 ? s after sc_en has been set to ?1?, the encoder stops writing data, and the decoder stops and then outputs no-tone data. 4) error processing receive error: in the figure above, an example of a receive error occurrence is shown in the write valid segment we4. if data writing is not completed within a write valid segment, rx_err is set to ?1? and an interrupt is generated. the state o f rx_err will be maintained during and after the next write valid segment until just before the end of a frame that has been written normally into the rx buffer. if an error occurs in the write valid segment we4, data generated according to the plc algorithm specified in g.711 appendix i is output during the decoder output segment r4. however, if the g.711 pcl function has been set disabled, no-tone data will be output. transmit error: in the figure above, an example of a transmit error occurrence is shown in the read valid segment re5. if data reading is not completed within a read valid segment, tx_err is set to ?1? and an interrupt is generated. the state of tx_err will be maintained during and after the next read valid segment until just before the end of a frame that has been read normally from the transmit buffer. even if data reading is not completed, the data in th e transmit buffer is updated as usual. 5) start interval an interval of 10.0 ms or more is required after the speech codec has stopped before it is started again. during this interval , it is possible to change the speech codec. write valid segment: there is no restriction of time on the first write valid segment (we1) after the speech codec is started. for the write valid segment we2, complete the writing of data to the rx buffer within 4.0 ms from the falling edge of fr1b. for the write valid segment we3 and after, complete the writing of data to the rx buffer within 9.0 ms from the falling edge o f fr1b. read valid segment: complete the reading of data from the tx buffer within 9.0 ms from the falling edge of fr0b.
fedl7074-003-01 ML7074-004 31/98 d. g.711 ( ? -law, a-law) (20 ms/frame mode) fig. 18 g.711 ( ? -law, a-law) control timing (20 ms/frame mode) fr0b (output) read out by mcu read out valid segment 4) error tx_err (cr3-b1) 20 ms enc speech codec t1 t3 t5 t9 t7 stopped/init t1 sc_en (cr2-b7) 1) start maximum 250 ? s 2) operating 3) stop maximum 250 ? s 5) start interval 10.0 ms or more stopped/ init re1 re3 re5 re7 speech codec fr1b (output) write in by mcu write valid segment we1 intb (output) rx_err (cr3-b0) t wait dec_outon (cr2-b5) 20 ms no-tone output/init dec out r5(plc) r7 r9 r1 r3 no-tone output/init no- tone about 3.75 ms 20 ms we3 about 125 ? s we5 we7 we9 we11 4) error about 125 ? s 1) start dec_outon ?0?, sc_en ?0? ? ?1? the speech codec starts within about 250 ? s after sc_en has been set to ?1?. the encoder starts in the already initialized condition and starts encoding immediately aft er the speech codec has been started. the decoder carries out initialization after the speech codec has been started, and outputs no-tone data. if the first receive data has been written and the twait wait time has elapsed, the dec output control bit (dec_outon) can be set to ?1?. after setting dec_outon to ?1?, the decoder outputs no-tone data for about 3.75 ms, and then starts decoder output. however, if the plc function has been disabled, the decoder starts decoder output after setting dec_out_on to ?1?. 2) operating the data encoded during encode segment tn is read by the mcu during read valid segment ren. this operation is repeated until the speech codec is stopped (n = 1, 3, 5, ?). the data written by the mcu during write valid segment wen is output during decoder output segment rn. this operation is repea ted until the speech codec is stopped (n = 1, 3, 5, ?). 3) stop set sc_en ?1? ? ?0?, dec_outon ?1? ? ?0? encoding and decoding after the stoppage of the speech codec is disabled. within about 250 ? s after sc_en has been set to ?1?, the encoder stops writing data, and the decoder stops and then outputs no-tone data. 4) error processing receive error: in the figure above, an example of a receive error occurrence is shown in the write valid segment we5. if data writing is not completed within a write valid segment, rx_err is set to ?1? and an interrupt is generated. the state o f rx_err will be maintained during and after the next write valid segment until just before the normal end of a frame that has been written into the rx buffer. if an error occurs in the write valid segment we5, data generated according to the plc algorithm specified in g.711 appendix i is output during the decoder output segment r5. however, if the g.711 pcl function has been set disabled, no-tone data will be output. transmit error: in the figure above, an example of a transmit error occurrence is shown in the read valid segment re5. if data reading is not completed within a read valid segment, tx_err is set to ?1? and an interrupt is generated. the state of tx_err will be maintained during and after the next read valid segment until just before the normal end of a frame that has been read from the transmit buffer. even if data reading is not completed, the data in the transmit buffer is updated as usual. 5) start interval an interval of 10.0 ms or more is required after the speech codec has stopped before it is started again. during this interval , it is possible to change the speech codec. write valid segment: there is no restriction of time on the first write valid segment (we1) after the speech codec is started. for the write valid segment we3, complete the writing of data to the rx buffer within 15.0 ms from the falling edge of fr1b. for the write valid segment we5 and after, complete the writing of data to the rx buffer within 18.0 ms from the falling edge of fr1b. read valid segment: complete the reading of data from the tx buffer within 18.0 ms from the falling edge of fr0b.
fedl7074-003-01 ML7074-004 32/98 method of controlling control registers the method of controlling the control registers is shown in fig. 19. this lsi contains 21 control registers cr0 to cr20 for carrying out various controls. further, the control bit (cr1-b7) assigned within such a control register, the address (cr6, cr7), and the data (cr8, cr9) are used to modify and control the data memory inside the dsp in this lsi. see the section on ?method of accessi ng and controlling the internal data memory? for details on how to access the data memory inside the dsp of this lsi. the higher two bits of the address of a control register will be ?0?. irrespective of the 16-bit or 8-bit data width selected in cr11-b5 (16b/8b), all contro l operations of control registers are made with an 8-bit data width using only data bits d7 to d0. when the data bus is being accessed in the 16-bit access mode, data bits d15 to d8 are configured as inputs while the data is written to the contro l register, and are configured as outputs while the data is read from the control register. when a control register write is being made, ?1? or ?0? is input to d15 to d8, and ?1? is read out during a control register read. fig. 19 method of controlling the control registers a7-a0 d7-d0 csb wrb rdb write read address data address data address = 00xxxxxxb
fedl7074-003-01 ML7074-004 33/98 method of accessing transmit and receive buffers a. in the frame mode (cr11-b7 = ?0?) the control timing and the method of accessing the transmit buffer (tx buffer) during the frame mode are shown in fig. 20. when the transmit buffer, which stores the compressed speech data of the transmit side (the speech compressing side), becomes full, a read request is made to the mpu by taking fr0b from the ?h? state to the ?l? state. read the data in the transmit buffer during the following timing. the read address of the transmit buffer during the following timing. the read address of the tran smit buffer is ?10xxxxxxb? in which the lower 6 bits are ignored. further, fr0b will be maintained in the ?l? st ate until all the data bytes in the transmit buffer are read out. fig. 20 transmit buffer control timing the control timing of the receive buffer (r x buffer) in the frame mode is shown in fig. 21. a write request is made to the mpu by taking fr1b from the ?h? state to the ?l ? state indicating that the r eceive buffer for storing the speech compression data of the receive si de (the speech decompression side) has become empty. write data into the receive buffer at the following tim ing. the write address of the receive buffer is ?01xxxxxxb? in which the lower 6 bits are ignored. further, fr1b will be mainta ined in the ?l? state until the receive buffer is written to become full. fig. 21 receive buffer control timing a7-a0 d15-d0 csb wrb rdb address data 0 address fr0b data n-1 address = 10xxxxxxb (fixed) number of data = n words (transmit buffer full) (transmit buffer empty) a7-a0 d15-d0 csb wrb rdb address data 0 address fr1b data n-1 address = 01xxxxxxb (fixed) number of data = n words (receive buffer empty) (receive buffer full)
fedl7074-003-01 ML7074-004 34/98 b. in the dma mode (cr11-b7 = ?1?) the control timing of the transmit buffer in the dma mode is shown in fig. 22. a dma request is made to the mpu by taking dmarq0b from the ?h? state to the ?l ? state when the transmit buffer storing the compressed speech data of the transmit side (the speech compressing side) becomes full. after the dma request is made, an acknowledgement is input by changing the acknowledgement signal dmaack0b to ?0? fr om ?1?, and also, this dmarq0b will be cleared automatically (?l? ? ?h?) when a falling edge of th e read enable si gnal is accepted (rdb = ?1? ? ?0?). read the data in the transmit buffer at the following timing simultaneously with the acknowledgement input. dmarq0b repeats the dma request until all the data in the transmit buffer has been read out. fig. 22 transmit buffer control timing in the dma mode the control timing of the receive buffer during the dma transfer mode is shown in fig. 23. a dma transfer request is made to the mpu by taking dmarq1b from the ?h? state to the ?l? state when the receive buffer for storing the speech compression data of the receive side (the speech decompression side) has become empty. after the dma transfer request is made, an acknowledgem ent is input by changing the acknowledgement signal dmaack1b from ?1? to ?0?, and al so, this acknowledgement signal dmaack1b will be cleared automatically (?l? ? ?h?) when a falling edge of the read enable signal is accepted (rdb = ?1? ? ?0?). write data into the receive buffer at the following timi ng simultaneously with the acknowledge ment input. dmarq1b repeats the dma transfer request until data has been writte n into the receive buffer to make it full. fig. 23 receive buffer control timing in the dma mode a7-a0 d15-d0 address data 0 address dmarq0b data n-1 address = 10xxxxxb (fixed) number of data = n words (transmit buffer full) (transmit buffer empty) dmaack0b wrb rdb a7-a0 d15-d0 wrb rdb address data 0 address dmarq1b data n-1 address = 01xxxxxxb (fixed) number of data = n words (receive buffer empty) (receive buffer full) dmaack1b
fedl7074-003-01 ML7074-004 35/98 control registers table 4 shows a map of the control registers. cr6 to cr9 are used for accessing the data memory inside the dsp. in addition, the changeable mode of operation is show n below the name of the register assigned to each bit. table 4 map of control registers address contents reg name a7 to a0 b7 b6 b5 b4 b3 b2 b1 b0 r/w spdn # afe_en # # # long/ short ope _stat cr0 00h /e ? i/ ? ? ? i/ i/ r/w xdmwr xdmrd # # # # # # cr1 01h i/e i/e ? ? ? ? ? ? r/w sc_en fgen _en dec_ outon tdet1 _en tdet0 _en dtmf _en ec_en # cr2 02h i/e i/e /e i/e i/e i/e i/e ? r/w dsp _err # # tone1 _det tone0 _det # tx _err rx _err cr3 03h ? ? ? ? ? ? ? ? r/ int dp_det # dtmf _det dtmf_ code3 dtmf_ code2 dtmf_ code1 dtmf_ code0 cr4 04h ? ? ? ? ? ? ? ? r/ ready # # # # # # fgen _flag cr5 05h ? ? ? ? ? ? ? i/e r/w internal data memory access (higher address) a15 a14 a13 a12 a11 a10 a9 a8 cr6 06h i/e /w internal data memory access (lower address) a7 a6 a5 a4 a3 a2 a1 a0 cr7 07h i/e /w internal data memory access (higher data)) d15 d14 d13 d12 d11 d10 d9 d8 cr8 08h i/e r/w internal data memory access (lower data)) d7 d6 d5 d4 d3 d2 d1 d0 cr9 09h i/e r/w # dpdet _en # tdet1 _sel tdet0 _sel vfro1 _sel vfro0 _sel ain _sel cr10 0ah ? i/e ? i/ i/ i/e i/e i/e r/w frame/ dma 10ms /20ms 16b /8b # # sc _sel1 sc _sel0 g711_ plcdis cr11 0bh i/ i/ i/ ? ? i/e i/e i/e r/w
fedl7074-003-01 ML7074-004 36/98 # # # # # psc _sel1 psc _sel0 pcmif _en cr12 0ch ? ? ? ? ? i/e i/e i/ /w cr13 0dh $ $ $ $ $ $ $ $ / cr14 0eh $ $ $ $ $ $ $ $ / ta2 ta1 ta0 $ $ $ $ $ cr15 0fh i/ i/ i/ ? ? ? ? ? r/w # # # # # # gpi1 gpi0 cr16 10h ? ? ? ? ? ? ? ? r/ # # # # # # gpo1 gpo0 cr17 11h ? ? ? ? ? ? i/e i/e r/w fgen _d7 fgen _d6 fgen _d5 fgen _d4 fgen _d3 fgen _d2 fgen _d1 fgen _d0 cr18 12h i/e r/w tgen0 _rx tgen0 _tx tgen0 _cnt5 tgen0 _cnt4 tgen0 _cnt3 tgen0 _cnt2 tgen0 _cnt1 tgen0 _cnt0 cr19 13h i/e r/w tgen1 _rx tgen1 _tx tgen1 _cnt5 tgen1 _cnt4 tgen1 _cnt3 tgen1 _cnt2 tgen1 _cnt1 tgen1 _cnt0 cr20 14h i/e r/w ? 15h-3fh $ $ $ $ $ $ $ $ / notes: register names #: reserved bit. do not change the initial value of ?0?. $: access-prohibited bit. do not read or write this bit. changeable operating mode: i/e: can be changed in either the initialization mode or the operating mode. i/: can be changed only in the initialization mode. /e: can be changed only in the operating mode. r/w r/w: both read and write are possible. /w: write only r/: read only /: access prohibited notice: since the reading is made in synchronization with the s ync signal (8 khz) when the following control registers are set in the operating mode, maintain the condition for 250 ? s or more. cr1, cr2, cr5, cr10, cr11, cr12, cr19, cr20 see the method of accessing and contro lling the internal data memory for the method of setting the following control registers. cr6, cr7, cr8, cr9
fedl7074-003-01 ML7074-004 37/98 (1) cr0 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr0 spdn # afe _en # # # long/ short ope _stat mode in which the setting can be changed /e ? i/ ? ? ? i/ i/ initial value 0 0 0 0 1* 0 0 0 r/w b7: software power down reset control 0: normal operation mode 1: power down reset the power down reset state can be initiated by setting this bit to ?1? for 200 ns or longer. during the power down reset, all the contents of the control register s and of the internal data memory will be cleared automatically. the power down reset state is released by setting this bit to ?1? first and then resetting it to ?0?. b6: reserved bit. do not change the initial value. b5: analog front-end power down control 0: normal operation mode 1: power down state (excluding avref) when using the pcm i/f mode, it is recommended to set this bit to ?1? since the analog front-end function is not used in these modes. in addition, when setting this bit to ?1?, simultaneously set the vfro0 and vfro1 outputs to the avref side (cr10-b2, b1 = ?0?). b4-2: reserved bits. do not change the initial values. b1: sync frame control 0: long frame synchronization signal 1: short frame synchronization signal b0: operation start control 0: operation hold 1: operation start the initialization mode is entered after releasing the power down reset state. in the initialization mode, it becomes possible to modify the contents of the control registers and the in ternal data memory. read out the ready bit (cr5-b7) repeatedly and start modifying the co ntents of the control registers and the internal data memory after detecting a ?1? in this bit. when this bit is set to ?1? after completing the writing of data in the control registers and the internal data memory, the lsi goes into the ready state (cr5-b7 = ?0?) and the normal operation mode is initiated. carry out modifications of the control registers and the internal data memory after changing to the normal operation mode. the method of changing the contents of the internal data memory is described later. the flowchart of the initialization mode is shown in fig. 24. note: * although the initial value of this bit is ?0?, it will be set to ?1? automatically before starting the initialization mode. further, a ?0? will be set in this bit auto matically after the initialization mode if pcmif_en (cr12-b0) is ?1?. when setting this register, make sure that the above value is not changed.
fedl7074-003-01 ML7074-004 38/98 fig. 24 initialization mode flowchart initialization mode pdnb = 0 or spdn = 1 pdnb = 1 & spdn = 0 ope_stat(cr0-b0) = 1 default storage memory change normal operation start initialization mode power down state released ready(cr5-b7) = 1 ready(cr5-b7) = 0 power down state wait of about 1.0 s internal lsi initialization external setting internal lsi automatic processing normal operation mode control register setting control register access and internal data memory access prohibited segment cr15 = 40h
fedl7074-003-01 ML7074-004 39/98 (2) cr1 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr1 xdmwr xdmrd # # # # # # mode in which the setting can be changed i/e i/e ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 r/w b7: internal data memory write control 0: write stopped 1: write the data set in cr8 and cr9 (d15 to d0) is written into the internal data memory at the address set in cr6 and cr7 (a15 to a0). when this writing is completed, th is bit is automatically cleared to ?0?. when writing data successively, make the settings after confirming that this bit is ?0?. for details of the method of controlling the internal memory, see the section on the method of accessing and controlling the internal data memory later in this booklet. b6: internal data memory read control 0: read stopped 1: read the data in the internal data memory at the address set in cr6 and cr7 (a15 to a0) can be read out from cr8 and cr9 (d15 to d0). when this reading is completed, this bit is cleared to ?0? automatically. when reading out data successively, read the data after confirming that this bit has become ?0?. for details of the method of controlling the internal memory, see the section on the method of accessing and controlling the internal data memory later in this booklet. notice: it is not possible to carry out simultaneously the above internal memory read and write controls. the setting of cr1-b7 and cr1-b6 = ?11? is prohibited and should never be made. b5 to b0: reserved bits. prohibited to change the initial settings.
fedl7074-003-01 ML7074-004 40/98 (3) cr2 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr2 sc_en fgen _en dec_ outon tdet1 _en tdet0 _en dtmf _en ec_en # mode in which the setting can be changed i/e i/e /e i/e i/e i/e i/e ? initial value 0 0 0 0 0 0 0 0 r/w b7: speech codec control register 0: speech codec stopped the encoder stops and the storing of data in the transmit buffer is stopped. the decoder stops and no-tone data is output continuously. it is possible to change th e speech data compression coding method when the speech codec has stopped. 1: speech codec operated the speech codec starts operating when this bit is set to ?1?. the speech codec starts after carrying out its own initialization. note: when stopping the speech codec by setting sc_en to ?0 ?, set dec_outon to ?0? at the same time. in addition, when starting the speech codec by setting sc _en to ?1?, make sure that dec_outon has been set to ?0?. b6: fsk_gen control register 0: fsk_gen stopped 1: fsk_gen operated the operation is started by setting this bit to ?1?. for more information about the control method, see the fsk generator subsection in the method of accessing and controlling internal data memory section described later. b5: decoder output control register this bit controls the first decoder output timing after the speech codec is started. after the speech codec is started, if the first receive data has been written and the twait wait time has elapsed, this bit can be set to ?1?. when this bit is set to ?1?, the decoder output starts depending on the coding format of the selected sp eech codec, as shown below. when g.711 ( ? -law/a-law) is selected: if the plc function is enabled, no-tone data about 3.75 ms long is output after this bit is set to ?1?. then, decoder output starts. if the plc function is disabled, the decoder output starts after this bit is set to ?1?. when g.729.a is selected: the decoder output starts about 15 ms after this bit is set to ?1?. in addition, when stopping the speech codec by setting sc_en to ?0?, set this bit also to ?0? at the same time. for more information about the control method, see figures 15 through 18 in the transmit and receive buffer control method section. note: at least 1 ms of the twait wait time is re quired after the speech codec has been started. b4: tone_det1 detector control register 0: tone_det1 stopped 1: tone_det1 operated the operation is started by setting this bit to ?1?. a ?1? is set to tone_det1 (cr3-b4) during the period when a 2100 hz* tone is being detected.
fedl7074-003-01 ML7074-004 41/98 b3: tone_det0 detector control register 0: tone_det0 stopped 1: tone_det0 operation the operation is started by setting this bit to ?1?. a ?1? is set to tone_det0 (cr3-b3) during the period when a 1650 hz* tone is being detected. remarks: * it is possible to change the detect frequencies. contact rohm's responsible sales person if you wish to change these frequencies. b2: dtmf detector control register 0: dtmf detect function stopped 1: dtmf detect function operated b1: echo canceller control register 0: echo canceller function stopped (the echo canceller is put in the through mode) 1: echo canceller function active remarks: the operation is started after the echo canceller internal coefficients cleared. b0: reserved bit. prohibited to change the initial setting.
fedl7074-003-01 ML7074-004 42/98 (4) cr3 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr3 dsp _err # # tone1 _det tone0 _det # tx _err rx _err mode in which the setting can be changed ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 r/ b7: dsp status register 0: normal operation state 1: abnormal operation state this lsi has a built-in watchdog timer, and when the program of the dsp section goes into uncontrollable execution state due to external distur bances around this lsi or due to pow er supply abnormalities, etc., the dsp_err status will be set to ?1? and an interrupt will be generated. when this bit becomes ?1?, carry out a power down reset using either pdnb or spdn of cr0-b7. this bit gets cleared by a power down reset operation. notice: the dsp_err status cannot detect all abnormal operation conditions. the abnormality will not be detected even when the dsp goes into uncontrolled program execution if the watchdog timer gets cleared during that program execution. b6, b5: reserved bit. prohibited to change the initial setting. b4: tone1 detector detect status register 0: not detected 1: detected b3: tone0 detector detect status register 0: not detected 1: detected b2: reserved bit. prohibited to change the initial setting. b1: transmit buffer status register 0: transmit buffer in normal operation state 1: transmit buffer in error state this bit becomes ?1? when an overrun error occurs in the transmit buffer, and will be ?0? otherwise. b0: receive buffer status register 0: receive buffer in normal operation state 1: receive buffer in error state this bit becomes ?1? when an underflow error occurs in the receive buffer, and will be ?0? otherwise. an interrupt is generated whenever there is a change in the state of any of the above bits (?0? ? ?1? or ?1? ? ?0?).
fedl7074-003-01 ML7074-004 43/98 (5) cr4 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr4 int dp_det # dtmf _det dtmf_ code3 dtmf_ code2 dtmf_ code1 dtmf_ code0 mode in which the setting can be changed ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 r/ b7: interrupt generation status register this is a directly coupled register with the logic of in tb inverted. a ?1? will be read out from this bit when intb is ?l? and will be ?0? otherwise. 0: during the period intb is ?h? 1: during the period intb is ?l? notice: the statuses of the int bit and intb may not be the same when a dsp_err is generated. b6: dial pulse detector detect status register this bit indicates the detect status of the dial pulse detector. this bit becomes ?1? during the period when a dial pulse is being detected and will be ?0? otherwise. 0: dial pulse not detected 1: dial pulse detected b5: reserved bit. prohibited to change the initial value.
fedl7074-003-01 ML7074-004 44/98 b4: dtmf detector detect status register this bit indicates the detect status of the dtmf detector. this bit becomes ?1? during the period when a dtmf signal is being detected and will be ?0? otherwise. 0: no dtmf signal detected 1: dtmf signal detected b3 to b0: dtmf code indication registers when dtmf_en (cr2-b2) has been set to ?1?, a valid dtmf code is stored in these bits during the period a dtmf signal is being detected (cr4-b4 dtmf_det = ?1?). these bits output the data ?0000? when no dtmf signal is detected (dtmf_det = ?0 ?). the codes are listed in table 5. table 5 dtmf detect code table dtmf_3 dtmf_2 dtmf_1 dtmf_0 low frequency [hz] high frequency [hz] dial number 0 0 0 0 697 1209 1 0 0 0 1 770 1209 4 0 0 1 0 852 1209 7 0 0 1 1 941 1209 * 0 1 0 0 697 1336 2 0 1 0 1 770 1336 5 0 1 1 0 852 1336 8 0 1 1 1 941 1336 0 1 0 0 0 697 1477 3 1 0 0 1 770 1477 6 1 0 1 0 852 1477 9 1 0 1 1 941 1477 # 1 1 0 0 697 1633 a 1 1 0 1 770 1633 b 1 1 1 0 852 1633 c 1 1 1 1 941 1633 d an interrupt is generated whenever there is a change in the statuses of the bits b6, b4 to b0 above (?0? ? ?1? or ?1? ? ?0?).
fedl7074-003-01 ML7074-004 45/98 (6) cr5 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr5 ready # # # # # # fgen _flag mode in which the setting can be changed. ? ? ? ? ? ? ? i/e initial value 0 0 0 0 0 0 0 0 r/w b7: initialization mode indication register 0: other than the initialization mode 1: initialization in progress after the power down reset state is released, this lsi en ters the initialization mode. this bit will be set to ?1? in the initialization mode. b6 to b1: reserved bits. prohibited to change the initial settings. b0: fsk output data setup completion flag after writing data into the fsk output data setup register (cr18), set this bit to ?1?. once the written data is read into the internal buffer of the fsk signal generation bl ock, this bit is automatically cleared to ?0?, and an interrupt is generated at the same time. do not write to cr5 when this bit is ?0?. an interrupt is generated when there is a change in bit b0 (?1? ? ?0?).
fedl7074-003-01 ML7074-004 46/98 (7) cr6 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr6 a15 a14 a13 a12 a11 a10 a9 a8 mode in which the value can be changed i/e initial value 0 0 0 0 0 0 0 0 /w b7 to b0: higher order address of the internal data memory these bits are the registers for setting the higher order byte of the address in the internal data memory. for details on the method of writing, see the section on the method of accessing and controlling the internal data memory (8) cr7 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr7 a7 a6 a5 a4 a3 a2 a1 a0 mode in which the value can be changed i/e initial value 0 0 0 0 0 0 0 0 /w b7 to b0: lower order address of the internal data memory these bits are the registers for setting the lower order by te of the address in the internal data memory. for details on the method of writing, see the section on the method of accessing and controlling the internal data memory. (9) cr8 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr8 d15 d14 d13 d12 d11 d10 d9 d8 mode in which the value can be changed i/e initial value 0 0 0 0 0 0 0 0 r/w b7 to b0: higher order data of the internal data memory these bits are the registers for setting the higher order byte of the data in the internal data memory. for details on the method of writing and reading, see th e section on the method of accessing and controlling the internal data memory. (10) cr9 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr9 d7 d6 d5 d4 d3 d2 d1 d0 mode in which the value can be changed i/e initial value 0 0 0 0 0 0 0 0 r/w b7 to b0: lower order data of the internal data memory these bits are the registers for setting the lower order by te of the data in the internal memory. for details on the method of writing and reading, see the s ection on the method of accessing and controlling the internal data memory.
fedl7074-003-01 ML7074-004 47/98 (11) cr10 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr10 # dpdet_ en # tdet1_ sel tdet0_ sel vfro1 _sel vfro0 _sel ain _sel mode in which the value can be changed ? i/e ? i/ i/ i/e i/e i/e initial value 0 0 0 0 0 0 0 0 r/w b7: reserved bit. prohibited to change the initial setting. b6: dial pulse detector control register 0: dial pulse detector stopped 1: dial pulse detector active b5: reserved bit. prohibited to change the initial setting. b4: tdet1 detect path select register 0: transmitting section 1: receiving section b3: tdet0 detect path select register 0: transmitting section 1: receiving section b2: vfro1 selection 0: avref (output of about 1.4 v) 1: receiver side speech output b1: vfro0 selection 0: avref (output of about 1.4 v) 1: receiver side speech output b0: input amplifier selection 0: selection of amp0 1: selection of amp1
fedl7074-003-01 ML7074-004 48/98 (12) cr11 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr11 frame/ dma 10ms /20ms 16b /8b # # sc _sel1 sc _sel0 g711_ plcdis mode in which the value can be changed i/ i/ i/ ? ? i/e i/e i/e initial value 0 0 0 0 0 0 0 0 r/w b7: frame/dma select register 0: frame access 1: dma slave interface access this bit selects the method of accessi ng the transmit and receive buffers. the initial value is frame access. b6: 10 ms/20 ms select register 0: 10 ms 1: 20 ms this bit selects the buffering time of the transmit and receive buffer s. the initial value is 10 ms. b5: mcu interface data width select register 0: 16-bit data width interface 1: 8-bit data width interface this bit selects the width of the data bus connected to the transmit and receive buffers. the initial value is 16 bits. when the 8-bit bus width is used, tie d15 to d8 to either ?1? or ?0?. b4, b3: reserved bits. prohibited to change the initial values. b2, b1: speech codec select registers - when using the analog i/f mode, (0, 0): g.729.a (0, 1): g.711 ( ? -law) (1, 0): prohibited (1, 1): g.711 (a-law) the speech codec can be selected wh en cr2-b7 (sc_en) is in the ?0? st ate. prohibited to change the speech codec when it is operating. - when using the pcm i/f mode (cr12-b0 = ?1?), these bits select the pcm i/f coding method. further, the speech codec select bits will be cr12-b2 and cr12-b1. (0, 0): 16-bit linear (2?s complement format) (0, 1): g.711 ( ? -law) (1, 0): prohibited (1, 1): g.711 (a-law) the coding method can be selected wh en cr2-b7 (sc_en) is in the ?0? state. prohibited to change the coding method during operation. b0: g.711 plc function disable control register setting this bit to ?1? disables the g.711 plc function. if the g.711 plc function is disa bled, no-tone data is output when a receive error occurs. 0: enable 1: disable this bit can be enabled or disabled when cr2-b7 (sc_ en) is ?0?. change of setting during operation is prohibited.
fedl7074-003-01 ML7074-004 49/98 (13) cr12 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr12 # # # # # psc _sel1 psc _sel0 pcmif _en mode in which the value can be changed ? ? ? ? ? i/e i/e i/ initial value 0 0 0 0 0 0 0 0 /w b7 to b3: reserved bits. prohibited to change the initial settings. b2, b1: speech codec select registers in the pcm i/f mode (0, 0): g.729.a (0, 1): g.711 ( ? -law) (1, 0): prohibited (1, 1): g.711 (a-law) the speech codec type can be select ed when cr2-b7 (sc_en) is in the ?0? state. prohibited to change the speech codec type during operation. b0: pcm i/f mode control register 0: analog i/f mode set the speech codec type selection in cr11-b2 and cr11-b1. 1: pcm i/f mode set the pcm/if coding method in cr11-b2 and cr11-b1, and set the speech codec type selection in b2 and b1 of this register. (14) cr13 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr13 $ $ $ $ $ $ $ $ mode in which the value can be changed ? ? ? ? ? ? ? ? initial value ? ? ? ? ? ? ? ? / b7 to b0: reserved bits. prohibited to change the initial settings. (15) cr14 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr14 $ $ $ $ $ $ $ $ mode in which the value can be changed ? ? ? ? ? ? ? ? initial value ? ? ? ? ? ? ? ? / b7 to b0: reserved bits. prohibited to change the initial settings.
fedl7074-003-01 ML7074-004 50/98 (16) cr15 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr15 ta2 ta1 ta0 $ $ $ $ $ mode in which the value can be changed i/ i/ i/ ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 r/w b7 to b5: registers for adjustment set to ?010? at the beginning of the initialization mode. (0, 1, 0): fixed b4 to b0: reserved bits. prohibited to change the initial settings. (17) cr16 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr16 # # # # # # gpi1 gpi0 mode in which the value can be changed ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 ? ? r/ b7 to b2: reserved bits. prohibited to change the initial settings. b1: gpi1 level read out register 0: gpi1 level is ?0?. 1: gpi1 level is ?1?. b0: gpi0 level read out register 0: gpi0 level is ?0?. 1: gpi0 level is ?1?. note: gpi0 is used as the input of the dial pulse detector in the secondary functions. it is possible to read out gpi0 even when the dial pulse detector is operating.
fedl7074-003-01 ML7074-004 51/98 (18) cr17 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr17 # # # # # # gpo1 gpo0 mode in which the value can be changed ? ? ? ? ? ? i/e i/e initial value 0 0 0 0 0 0 0 0 r/w b7 to b2: reserved bits. prohibited to change the initial settings. b1: gpo1 output level register 0: ?l? level is output at gpo1. 1: ?h? level is output at gpo1. b0: gpo0 output level register 0: ?l? level is output at gpo0. 1: ?h? level is output at gpo0. notice: gpo0 is used in the secondary functions as the output of the dial pulse transmitter. note that it is prohibited to change the content of the gpo0 bit when the dial pulse detector is operating. (19) cr18 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr18 fgen _d7 fgen _d6 fgen _d5 fgen _d4 fgen _d3 fgen _d2 fgen _d1 fgen _d0 mode in which the value can be changed i/e initial value 0 0 0 0 0 0 0 0 r/w b7 to b0: fsk transmit data setting registers
fedl7074-003-01 ML7074-004 52/98 (20) cr19 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr19 tgen0 _rx tgen0 _tx tgen0 _cnt5 tgen0 _cnt4 tgen0 _cnt3 tgen0 _cnt2 tgen0 _cnt1 tgen0 _cnt0 mode in which the value can be changed i/e initial value 0 0 0 0 0 0 0 0 r/w b7: tgen0 rx section output control register 0: output stopped. 1: tone output at the rx section b6: tgen0 tx section ou tput control register 0: output stopped. 1: tone output at the tx section b5: register for controlling addition or multiplication of tone a/b 0: addition (the tone a and tone b outputs are added.) 1: multiplication (the tone a and tone b outputs are multiplied.) b4: tone a/b output control register 0: onetime tone output the signal is output for a duration equal to the sum of tim_m0 and tim_m1 and then stopped. after stopping, cr19 will be cleared automatically within the lsi. 1: repetitive tone output the signal is output repeatedly as controlled by the time duration equal to the sum of tim_m0 and tim_m1. write 00h in this register cr19 in order to stop the signal output. notice: it is prohibited to write any value in this register other than 00h when repetitive output is being made. in the case of onetime tone output operation, make the next setting only after making sure that the content of this register has become 00h. when tone output is intended to resume after repetitive tone output is once ceased, the register setting must be made only after fade-out time plus 250 ? s. b3, b2: tone a output control registers 00: no tone is output. 01: the tone is stopped during the m0 period and is output during the m1 period. 10: the tone is output during the m0 period and stopped during the m1 period. 11: the tone is output during both the m0 and m1 periods. b1, b0: tone b output control registers 00: no tone is output. 01: the tone is stopped during the m0 period and is output during the m1 period. 10: the tone is output during the m0 period and is stopped during the m1 period. 11: the tone is output during both the m0 and m1 periods. note: although it is possible to output tone a and tone b alternately when the output controls of tone a and tone b are set in a mutually exclusive manner and their outputs are summed, the waveform after addition will be discontinuous since the phases of the two signals will be independent of each other.
fedl7074-003-01 ML7074-004 53/98 (21) cr20 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr20 tgen1 _rx tgen1 _tx tgen1 _cnt5 tgen1 _cnt4 tgen1 _cnt3 tgen1 _cnt2 tgen1 _cnt1 tgen1 _cnt0 mode in which the value can be changed i/e initial value 0 0 0 0 0 0 0 0 r/w b7: tgen1 pcm section output control register 0: output stopped. 1: tone output at the rx section b6: tgen1 tx section ou tput control register 0: output stopped. 1: tone output at the tx section b5: register for controlling addition or multiplication of tone c/d 0: addition (the tone c and tone d outputs are added.) 1: multiplication (the tone c and tone d outputs are multiplied.) b4: tone c/d output control register 0: onetime tone output the signal is output for a duration equal to the sum of tim_m0 and tim_m1 and then stopped. after stopping, cr20 will be cleared automatically within the lsi. 1: repetitive tone output the signal is output repeatedly as controlled by the time duration equal to the sum of tim_m0 and tim_m1. write 00h in this register cr20 in order to stop the signal output. notice: it is prohibited to write any value in this register other than 00h when repetitive output is being made. in the case of onetime tone output operation, make the next setting only after making sure that the content of this register has become 00h. when tone output is intended to resume after repetitive tone output is once ceased, the register setting must be made only after fade-out time plus 250 ? s. b3, b2: tone c output control registers 00: no tone is output. 01: the tone is stopped during the m0 period and is output during the m1 period. 10: the tone is output during the m0 period and stopped during the m1 period. 11: the tone is output during both the m0 and m1 periods. b1, b0: tone d output control registers 00: no tone is output. 01: the tone is stopped during the m0 period and is output during the m1 period. 10: the tone is output during the m0 period and is stopped during the m1 period. 11: the tone is output during both the m0 and m1 periods. note: although it is possible to output tone c and tone d alternately when the output controls of tone c and tone d are set in a mutually exclusive manner and their outputs are summed, the waveform after addition will be discontinuous since the phases of the two signals will be independent of each other.
fedl7074-003-01 ML7074-004 54/98 figure 25 shows block diagrams of the tone generation blocks (tone_gen0, tone_gen1). there is no difference in the tone generation method between tone_gen0 and tone_gen1. so, using tone_gen0 as an example, figure 26 shows the tone output control method, and figures 27 and 28 show the tone output control parameters. tgen0_freq_a tone_a tgen0_gain_a tgen0_gain_b tgen0_txgain_ total cr19-b5 tgen0_freq_b tone_b tgen0_rxgain_t otal tx rx [tone_gen0] tgen1_freq_c tone_c tgen1_gain_c tgen1_gain_d tgen1_txgain_ total cr20-b5 tgen1_freq_d tone_d tgen1_rxgain_ total tx rx [tone_gen1] fig. 25 tone generator section block diagram
fedl7074-003-01 ML7074-004 55/98 tone a, b frequency setting fade control setting (common to tone a and tone b) tone a/b/total gain setting cr19=xxx0xxxxb cr19 is cleared automatically within the lsi cr19=00000000b onetime tone output method tone a, b frequency setting fade control setting (common to tone a and tone b) tone a/b/total gain setting cr19=xxx1xxxxb set cr19=00000000b repetitive tone output method tone output stops repetitive output of tone stopping after onetime tone output tone a/b m0/m1 output control setting tone a/b m0/m1 output control setting fade-in step setting (common to tone a and tone b) fade-out step setting (common to tone a and tone b) fade-out time setting (common to tone a and tone b) fade-in step setting (common to tone a and tone b) fade-out step setting (common to tone a and tone b) fade-out time setting (common to tone a and tone b) "1" "0" "1" "0" * when tone output is intended to resume after repetitive tone output is once ceased, the register setting must be made only after fade-out time plus 250 ? s. m0/m1 output duration setting (common to tone a and tone b) m0/m1 output duration setting (common to tone a and tone b) fig. 26 tone output control method (in the case of tone_gen0)
fedl7074-003-01 ML7074-004 56/98 tim-m0 tim-m1 freq gain m0 on m1 on onetim tone output repetitive tone output output is made by repeating onetime tone output settings ??????????? gain tim-m0 tim-m1 freq m0 off m1 on tim-m0 tim-m1 m0 off m1 on tim-m0 tim-m1 freq m0 on m1 off tim-m0 tim-m1 freq m0 off m1 on fig. 27 tone output control parameters (in the case of tone_geno/tgen0_fade_cont off)
fedl7074-003-01 ML7074-004 57/98 fig. 28 tone output control parameters (in the case of tone_geno/tgen0_fade_cont ?on?) tim_m0 tim_m1 gain m0 on m1 on onetime tone output repetitive tone output ??????????? gain m0 off m1 on m0 off m1 on m0 on m1 off m0 off m1 on outputs a set of onetime tone output repetitively (tone_a and tone_b are output alternately.) ??????????? gain_ a m0 on m1 on m0 on m1 on tone_a tone_b tone_a tone_b gain_ b tim_m0 tim_m1 tim_m0 tim_m1 f-i f-o f-i f-o f-i f-o f-i f-o f-i f-o f-i f-o f-i f-o f-i f-o f-i f-o * "f-i" and "f-o" are times to fade in and to fade out respectively. parameters to determine them will be discussed later in this document.. outputs a set of onetime tone output repetitively (cr19="00h" is set in a way) ??????????? gain m0 off m1 on m0 off m1 on f-i f-o f-i f-o outputs a set of onetime tone output repetitively cr19="00h"
fedl7074-003-01 ML7074-004 58/98 method of accessing and controlling internal data memory writing method the four 8-bit registers cr6 to cr9 mapped within the se t of control registers are allocated to the following: 16-bit address of the internal data memory (a15 to a0) 16-bit data to be written (d15 to d0) the initialization mode is entered and a ?1? is set in cr5-b7 (ready) about 1.0 s after release from a power down reset due to pdnb or after a release from a software power down reset due to cr0-b7. in this writable state, after setting in cr6 to cr9 the inte rnal data memory address and the data to be written, if a ?1? is set in cr1-b7 (xdmwr), the writing of one word of data in the internal data memory will be completed. after completion of writing the data, cr 1-b7 will be cleared to ?0? automatic ally. the method of setting data in the internal data memory is shown in fig. 29. repeat the above operations for writing to several memory locations. when all the writing operations have been completed, the normal operations can be started by setting a ?1? in cr0-b0 (ope_stat). it is possible to re-write even in modes other than the in itialization mode the internal data memory locations related to gain control, tone transmission, ec, dpgen, and timer. even in such cases, carry out the updating of the internal data memory using the same method as described above. table 6 to table 9 list the internal data memory and related control registers. note: when data is set in the internal data memory during opera tion, since the reading is done in synchronization with the sync signal (8 khz), maintain the state for 250 ? s or more. fig. 29 method of setting data in the internal data memory cr8 (internal memory higher data) yes no cr1-b7, b6 = 0 updating internal memory cr1-b7 cleared automatically external setting automatic processing inside the lsi cr9 (internal memory lower data) cr7 (internal memory lower address) cr6 (internal memory higher address) cr1-b7(xdmwr) = 1 time duration from setting of cr1-b7 until it is cleared. in initialization mode: 20 ? s max. in normal operation: 250 ? s max. start writing
fedl7074-003-01 ML7074-004 59/98 reading method after setting the internal data memory address in cr6 and cr7 , one word of data from the internal data memory is stored in cr8 and cr9 when a ?1? is written in cr1-b 6 (xdmrd). after reading the data, cr1-b6 will be cleared to ?0? automatically. the method of reading the internal data memory is shown in fig. 30. further, the internal data memory read out can only be made for the internal data memory and the read only data memory within the related registers listed in table 6 to table 9. notice: when the internal data memory is read out during operati on, since the reading out is done in synchronization with the sync signal (8 khz), maintain the set address in the same state for 250 ? s or more. fig. 30 method of reading out internal data memory cr1-b6(xdmrd) = 1 yes no cr1-b6(xdmrd) = 0 external setting and read out cr8 (internal memory higher data) read out cr7 (internal memory lower address) cr6 (internal memory higher address) time duration from setting of cr1-b7 until it is cleared: in initialization mode: 20 ? s max. in normal operation: 250 ? s max. start read out cr9 (internal memory lower data) read out cleared automatically to "0" after the read out data is stored in cr8 and cr9. yes no cr1-b7, b6 = 0
fedl7074-003-01 ML7074-004 60/98 table 6 internal data memory and related control registers (1/4) initial value modes in which updating and read are possible function name internal data memory name address data data value in initializa- tion mode during idle state during operation transmit gain (txgain) 02ach 0080h 0 db y y y receive gain (rxgain) 02adh 0080h 0 db y y y side tone gain (stgain) 02aeh 0000h mute y y y gain fade control (gain_fade_cont) 02afh 0000h disabled y y n gain fade-in step (gain_fade_in_st) 02b0h 4c10h +1.5db y y *1 n gain control gain fade-out step (gain_fade_out_st) 02b1h 35d9h -1.5db y y *1 n tgen0 transmit control cr19 00h transmission stopped y y y tgen0 in-execution flag (tgen0_exe_flag) (read-only memory) 1141h 0000h not in execution y y y tone a frequency control (tgen0_freq_a) 1143h 0ccch 400 hz y y n tone b frequency control (tgen0_ freq_b) 1145h 007ah 15 hz y y n tone a gain control (tgen0_gain_a) 1147h 0080h ?13.3 dbm0 y y y tone b gain control (tgen0_gain_b) 1148h 0080h ?13.3 dbm0 y y y tgen0 time control 0 (tgen0_tim_m0) 1149h 0fa0h 500 ms y y n tgen0 time control 1 (tgen0_tim_m1) 114ch 0fa0h 500 ms y y n tgen0 rx section tone total gain (tgen0_rxgain_total) 1150h 0080h 0 db y y y tgen0 tx section tone total gain (tgen0_txgain_total) 1151h 0080h 0 db y y y tgen0 fade control (tgen0_fade_cont) 113bh 0000h disabled y y n tgen0 fade-in step (tgen0_fade_in_st) 113ch 47cfh +1db y y n tgen0 fade-out step (tgen0_fade_out_st) 113dh 390ah -1db y y n tgen0 fade-out time (tone0_fade_out_tim) 113eh 002bh 43 sync y y n tgen0 total gain fade control (tgen0_gain_total_fade_cont) 114dh 0000h disabled y y n tgen0 total gain fade-in step (tgen0_gain_total_fade_in_st) 114eh 4c10h +1.5db y y n tone genera- tion 0 tone_ gen0 tgen0 total gain fade-out step (tgen0_gain_total_fade_out_st) 114fh 35d9h -1.5db y y n *1 when gain fade is disabled
fedl7074-003-01 ML7074-004 61/98 table 7 internal data memory and related control registers (2/4) initial value modes in which updating and read are possible function name internal data memory name address data data value in initializa- tion mode during idle state during operation tgen1 transmit control cr20 00h transmission stopped y y y tgen1 in-execution flag (tgen1_exe_flag) (read-only memory) 1158h 0000h not in execution y y y tone c frequency control (tgen1_freq_c) 115ah 0ccch 400 hz y y n tone d frequency control (tgen1_ freq_d) 115ch 007ah 15 hz y y n tone c gain control (tgen1_gain_c) 115eh 0080h ?13.3 dbm0 y y y tone d gain control (tgen1_gain_d) 115fh 0080h ?13.3 dbm0 y y y tgen1 time control 0 (tgen1_tim_m0) 1160h 0fa0h 500 ms y y n tgen1 time control 1 (tgen1_tim_m1) 1163h 0fa0h 500 ms y y n tgen1 rx section tone total gain (tgen1_rxgain_total) 1167h 0080h 0 db y y y tgen1 tx section tone total gain (tgen1_txgain_total) 1168h 0080h 0 db y y y tgen1 fade control (tgen1_fade_cont) 1152h 0000h stopped y y n tgen1 fade-in step (tgen1_fade_in_st) 1153h 47cfh +1db y y n tgen1 fade-out step (tgen1_fade_out_st) 1154h 390ah -1db y y n tgen1 fade-out time (tone1_fade_out_tim) 1155h 002bh 43 sync y y n tgen1 total gain fade control (tgen1_gain_total_fade_cont) 1164h 0000h stopped y y n tgen1 total gain fade-in step (tgen1_gain_total_fade_in_st) 1165h 4c10h +1.5db y y n tone genera- tion 1 tone_ gen1 tgen1 total gain fade-out step (tgen1_gain_total_fade_out_st) 1166h 35d9h -1.5db y y n fsk output control (fgen_en) cr2-b6 0b stopped y y y fsk output data setting complete flag (fgen_flag) cr5-b0 0b writable y y y fsk output data setting register (fgen_d[7:0]) cr18 00h 00h y y y fsk generator fsk_ gen fsk gain control (fgen_gain) 02c4h 0080h ?13.3 dbm0 y y n
fedl7074-003-01 ML7074-004 62/98 table 8 internal data memory and related control registers (3/4) initial value modes in which updating and read are possible function name internal data memory name address data data value in initializa- tion mode during idle state during operation tone 0 control (tdet0_en) cr2-b3 0b stopped y y y main signal detect level control (tdet0_s_th) 1356h 1ebbh ?5.3 dbm0 y y n noise detect level control (tdet0_n_th) 136bh 1ebbh ?5.3 dbm0 y y n detect on guard timer control (tdet0_on_tm) 136ch 0028h 5 ms y y n detect off guard timer control (tdet0_off_tm) 136dh 0028h 5 ms y y n tone 0 detector tone_ det0 detect frequency (tdet0_freq) - - - - h - 1650 hz y n n tone 1 control (tdet1_en) cr2-b4 0b stopped y y y main signal detect level control (tdet1_s_th) 1382h 1ebbh ?5.3 dbm0 y y n noise detect level control (tdet1_n_th) 1397h 1ebbh ?5.3 dbm0 y y n detect on guard timer control (tdet1_on_tm) 1398h 0028h 5 ms y y n detect off guard timer control (tdet1_off_tm) 1399h 0028h 5 ms y y n tone 1 detector tone_ det1 detect frequency (tdet1_freq) - - - - h - 2100 hz y n n dtmf control (dtmf_en) cr2-b2 0b stopped y y y detect level control (dtmf_th) 0170h 1000h ?37.0 dbm0 y y n detect on guard timer control (dtmf_on_tm) 01d5h 00a0h 20 ms y y n detect off guard timer control (dtmf_off_tm) 01d7h 00a0h 20 ms y y n dtmf detector dtmf_ rec noise detect function control (dtmf_ndet_cont) 01d8h 0002h enabled y y n ec control (ec_en) cr2-b1 0b stopped y y y ec control (ec_cr) 002ch 0012h hd att off y y y echo canceller glpad control (glpad_cr) 002dh 000fh +6/?6 db y y n dial pulse detect control (dpdet_en) cr10-b6 0b stopped y y y detect on guard timer control (dpdet_on_tim) 0fcbh 0028h 5 ms y y n detect off guard timer control (dpdet_off_tim) 0fcch 0028h 5 ms y y n detect polarity control (dpdet_pol) 0fcah 0000h positive logic y y n end of detect timer control (dpdet_detoff_tim) 0fd1h 03e8h 125 ms y y n dial pulse detector dpdet detect code (dpdet_code) (read only data memory) 0fd3h 0000h not detected y y y dial pulse output control (dpgen_en) (can be read out) 0fbdh 0000h stopped y y y pulse count setting (dpgen_data) 0fbeh 0000h stopped y y n dial pulse speed control (dpgen_pps) 0fbfh 0000h 10 pps y y n dial pulse make ratio control (dpgen_duty) 0fc0h 0108h 33 ms y y n end of output control (dpgen_off_tim) 0fc2h 03e8h 125 ms y y n dial pulse generator dpgen output polarity control (dpgen_pol) 0fc3h 0000h positive logic y y n
fedl7074-003-01 ML7074-004 63/98 table 9 internal data memory and related control registers (4/4) initial value modes in which updating and read are possible function name internal data memory name address data data value in initializa- tion mode during idle state during operation timer control (tim_en) 0fb7h 0000h stopped y y y timer counter value display (tim_count) (read only data memory) 0fb8h 0000h count value 0000h y y y timer timer data setting (tim_data) 0fb9h ffffh max ffffh y y n outband control outband control (outband_control) 0fdah 0000h stopped y n n outband g.729.a data outband g.729.a data (outband_g729_dat) 00a6h 00a7h 00a8h 00a9h 00aah 7852h 80a0h 00fah c200h 07d6h ? y n n version lsi code display (ml7074_version) (read only data memory) 0152h 0003h ML7074-004 y y y note: initialization mode: the state after release from a power down reset, and in which the initial values of control registers and internal data memory can be altered. during idle state: the state in which the function given in the function name column has stopped. during operation: the state in which the function given in the function name column is operating.
fedl7074-003-01 ML7074-004 64/98 gain control (txgain, rxgain, stgain) it is possible to change the values of the transmit gain (txgain), receive gain (rxgain), and side tone gain (stgain). the positions of the respec tive gain controllers are the following. transmit gain (txgain): immediatel y before the speech codec input. receive gain (rxgain): immediatel y after the speech codec output. side tone gain (stgain): added to the input of the receiver section lpf fr om the output of the transmitter section bpf of the linear pcm codec. a. internal data memory for ad justing transmit gain (txgain) initial value: 0080h (0.0 db) when changing the gain value, compute it using the following equation: equation: 0080h ? gain example: making the gain +6 db ( ? 2): 0080h ? 2 = 0100h upper limit : about 40 db higher (data: 3200h) : 0 db (data: 0080h) lower limit : about ?42 db (data: 0001h) : mute (data: 0000h) b. internal data memory for ad justing receive gain (rxgain) initial value: 0080h (0.0 db) when changing the gain value, compute it using the following equation: equation: 0080h ? gain example: making the gain +6 db ( ? 2): 0080h ? 2 = 0100h upper limit : about 40 db higher (data: 3200h) : 0 db (data: 0080h) lower limit : about ?42 db (data: 0001h) : mute (data: 0000h) c. internal data memory for adjusting side tone gain (stgain) initial value: 0000h (mute) when changing the side tone gain value, compute it using the following equation: equation: 1000h ? gain example: making the gain ?20 db ( ? 0.1): 1000h ? 0.1 = 019ah upper limit : 0 db (data: 1000h) lower limit : about ?72 db (data: 0001h) : mute (data: 0000h)
fedl7074-003-01 ML7074-004 65/98 d. internal data memory for gain fade (gain_fade_cont) ?1? in b0 enables fade-in/-out in tx gain alternation; ?1? in b1 enables the function in rx gain alternation; and ?1? in b2 enables the function at muting in outband control. b7 b6 b5 b4 b3 b2 b1 b0 ? ? ? ? ? outband _fade_ cont rx_fade _cont tx_fade _cont initial value 0 0 0 0 0 0 0 0 initial value : 0000h (outband : disabled, rx : disabled, tx : disabled) b7, 6, 5, 4, 3 : reserved bits (prohibited to change the initial settings) b2 : outband_fade_cont 1 : on (fading-in/-out at muting and at un-muting) 0 : off b1 : rx_fade_cont 1 : on (fading-in/-out at rx gain alternation) 0 : off b0 : tx_fade_cont 1 : on (fading-in/-out at tx gain alternation) 0 : off e. internal data memory for gain fade-in step (gain_fade_in_st) initial value: 4c10h (+1.5db) when changing the step value, x, compute it using the following equation: equation: 10^(x/20)*16384 example: making the step value +3 db: 10^(3/20)*16384 = 23143d = 5a67h upper limit : about +6.0 db (data: 7fffh) lower limit : about +0.1 db (data: 40bdh) f. internal data memory forgain fade-out step (gain_fade_out_st) initial value: 35d9h (-1.5db) when changing the step value, x, compute it using the following equation: equation: 10^(x/20)*16384 example: making the step value -3 db: 10^(-3/20)*16384 = 11598d = 2d4eh upper limit : about -6.0 db (data: 2000h) lower limit : about -0.1 db (data: 3f44h) (note) step values for fade-in and fade-out can be determined independently; whereas the step values determined for fade-in and fade-out are common to tx gain, rx gain and outband_fade_cont.
fedl7074-003-01 ML7074-004 66/98 tone generator0 (tone_gen0) it is possible to set the various types of parameters of the tone generator block. a. internal data memory for tone frequency control tone_a (tgen0_freq_a) initial value: 0ccch (400 hz) tone_b (tgen0_freq_b) initial value: 007ah (15 hz) at the initial setting values a tone a of 400 hz and a tone b of 15 hz are output. use the following equation to compute the value of the setting when changing the frequency. equation: a ? 8.192 (a is the frequency to be set) example: to set a frequency of 2100 hz: 2100 ? 8.192 ? 4333h upper limit : 3 khz (data: 6000h) lower limit : 15 hz (data: 007ah) b. internal data memory for tone gain control tone_a (tgen0_gain_a) initial value: 0080h tone_b (tgen0_gain_b) initial value: 0080h the output level with the initial setting will be ?13.3 dbm0. use the following equation to compute the value of the setting when changing the gain. equation: 0080h ? gain example: for reducing the gain by 6 db ( ? 0.5): 0080h ? 0.5 = 0040h upper limit : 12 db more (data: 01fdh) lower limit : ?12 db less (data: 0020h) notice: make sure that the maximum amplitude does not exceed 3.17 dbm0 when the tones are multiplied or added.
fedl7074-003-01 ML7074-004 67/98 c. internal data memory for tone output time control (tgen0_tim_m0/tgen0_tim_m1) tgen0_tim_m0 (output time duration) initial value: 0fa0h (500 ms) tgen0_tim_m1 (output time duration) initial value: 0fa0h (500 ms) compute the value using the following equation when changing the time durations: equation: t/0.125 (t is the time duration in ms) example: when setting a time duration of 200 ms: 200/0.125 = 1600d = 0640h upper limit : 4095.875 ms (data: 7fffh) lower limit : 0.125 ms (data: 0001h) notice: it is prohibited to set a time duration of 0000h (0 ms) and hence be sure never to make such a setting. the tone output times set here are commonly valid for tone_a and tone_b, and cannot be determined differently. d. internal data memory for tone total gain control (tgen0_rxgain_total, tgen0_txgain_total) tgen0_rxgain_total initial value: 0080h tgen0_txgain_total initial value: 0080h the initial values will be 0 db. compute using the following equation when changing the output level. equation: 0080h ? gain example: decreasing the output level by 6 db: 0080h ? 0.5 = 0040h upper limit : 40 db higher (data: 3200h) lower limit : ?40 db lower (data: 0001h) : mute (data: 0000h) notice: the maximum amplitude should never exceed 1.3 vp-p. e. internal data memory for tgen0 fade control (tgen0_fade_cont) initial value: 0000h (disabled) ?0000h? in this data memory enables fade-in/-out with tone gain control. 0000h: fade-in/-out disabled 0001h: fade-in/-out enabled notice: when this fade-in/-out function is enabled, be sure that a corresponding fade-out step value and fade-out time are also set correctly.
fedl7074-003-01 ML7074-004 68/98 f. internal data memory for tgen0 fade-in step value control (tgen0_fade_in_st) initial value: 47cfh (+1.0db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-in step to +3db: 10^(3/20)*16384 = 23143d = 5a67h upper limit : about +6.0db (data: 7fffh) lower limit : about +0.1db (data: 40bdh) notice: the value set here are commonly valid for tone_a and tone_b, and cannot be determined differently. g. internal data memory for tgen0 fade-out step value control (tgen0_fade_out_st) initial value: 390ah (-1.0db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-out step to -3db: 10^(-3/20)*16384 = 11598d = 2d4eh upper limit : about -6.0db (data: 2000h) lower limit : about -0.1db (data: 3f44h) notice: the value set here are commonly valid for tone_a and tone_b, and cannot be determined differently. h. internal data memory for tgen0 fade-out time control (tgen0_fade_out_tim) initial value: 002bh (43 sync) compute using the following equation when changing the fade-out time. equation: 43db/?fade-out step value?[db] example: in a case with a fade-out step value 2db: 43/2 = 21d = 15h upper limit : 422 sync (data: 01a6h) lower limit : 8 sync (data: 0008h) notice: ?0000h? is prohibited to set. set a fade-out time ? tim_m0, tim_m1 the value set here are commonly valid for tone_a and tone_b, and cannot be determined differently. i. internal data memory for tgen0 total gain fade-out control (tgen0_gain_total_fade_cont) initial value: 0000h (disabled) ?0000h? in this data memory enables a function of total gain fade-in/-out for tx and rx. 0000h: disabled 0001h: enabled notice: the control of this function is commonly valid for tx and rx, and cannot be determined differently.
fedl7074-003-01 ML7074-004 69/98 j. internal data memory for fade-in step value control of tgen0 total gain (tgen0_gain_total_fade_in_st) initial value: 4c10h (+1.5db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-in step to +3db: 10^(3/20)*16384 = 23143d = 5a67h upper limit : about +6.0db (data: 7fffh) lower limit : about +0.1db (data: 40bdh) notice: the value set here are commonly valid for tx and rx, and cannot be determined differently. k. internal data memory for fade-out step value control of tgen0 total gain (tgen0_gain_total_fade_out_st) initial value: 35d9h (-1.5db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-out step to -3db: 10^(-3/20)*16384 = 11598d = 2d4eh upper limit : about -6.0db (data: 2000h) lower limit : about -0.1db (data: 3f44h) notice: step values can be set differently and parameters set are common to tgen0_txgain_total and tgen0_rxgain_total. l. internal data memory for tgen0 in-execution flag (tgen0_exe_flag) this address becomes ?0001h? when a tone generator is under operation. initial value: 0000h tone signal tgen0 state flag during execution tone signal cr19="00h" tgen0 state flag during execution tgen0_fade_cont = off tgen0_fade_cont = on cr19="00h"
fedl7074-003-01 ML7074-004 70/98 tone generator1 (tone_gen1) it is possible to set the various types of parameters of the tone generator block. a. internal data memory for tone frequency control tone_c (tgen1_freq_c) initial value: 0ccch (400 hz) tone_d (tgen1_freq_d) initial value: 007ah (15 hz) at the initial setting values a tone c of 400 hz and a tone d of 15 hz are output. use the following equation to compute the value of the setting when changing the frequency. equation: a ? 8.192 (a is the frequency to be set) example: to set a frequency of 2100 hz: 2100 ? 8.192 ? 4333h upper limit : 3 khz (data: 6000h) lower limit : 15 hz (data: 007ah) b. internal data memory for tone gain control tone_c (tgen1_gain_c) initial value: 0080h tone_d (tgen1_gain_d) initial value: 0080h the output level with the initial setting will be ?13.3 dbm0. use the following equation to compute the value of the setting when changing the gain. equation: 0080h ? gain example: for reducing the gain by 6 db ( ? 0.5): 0080h ? 0.5 = 0040h upper limit : 12 db more (data: 01fdh) lower limit : ?12 db less (data: 0020h) notice: make sure that the maximum amplitude does not exceed 3.17 dbm0 when the tones are multiplied or added.
fedl7074-003-01 ML7074-004 71/98 c. internal data memory for tone output time control (tgen1_tim_m0/tgen1_tim_m1) tgen1_tim_m0 (output time duration) initial value: 0fa0h (500 ms) tgen1_tim_m1 (output time duration) initial value: 0fa0h (500 ms) compute the value using the following equation when changing the time durations: equation: t/0.125 (t is the time duration in ms) example: when setting a time duration of 200 ms: 200/0.125 = 1600d = 0640h upper limit : 4095.875 ms (data: 7fffh) lower limit : 0.125 ms (data: 0001h) notice: it is prohibited to set a time duration of 0000h (0 ms) and hence be sure never to make such a setting. the tone output times set here are commonly valid for tone_a and tone_b, and cannot be determined differently. d. internal data memory for tone total gain control (tgen1_rxgain_total, tgen1_txgain_total) tgen1_rxgain_total initial value: 0080h tgen1_txgain_total initial value: 0080h the initial values will be 0 db. compute using the following equation when changing the output level. equation: 0080h ? gain example: decreasing the output level by 6 db: 0080h ? 0.5 = 0040h upper limit : 40 db higher (data: 3200h) lower limit : ?40 db lower (data: 0001h) : mute (data: 0000h) notice: the maximum amplitude should never exceed 1.3 vp-p. e. internal data memory for tgen1 fade control (tgen1_fade_cont) initial value: 0000h (disabled) ?0000h? in this data memory enables fade-in/-out with tone gain control. 0000h: fade-in/-out disabled 0001h: fade-in/-out enabled notice: when this fade-in/-out function is enabled, be sure that a corresponding fade-out step value and fade-out time are also set correctly, otherwise a pop noise might be generated at a tail.
fedl7074-003-01 ML7074-004 72/98 f. internal data memory for tgen1 fade-in step value control (tgen1_fade_in_st) initial value: 47cfh (+1.0db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-in step to +3db: 10^(3/20)*16384 = 23143d = 5a67h upper limit : about +6.0db (data: 7fffh) lower limit : about +0.1db (data: 40bdh) notice: the value set here are commonly valid for tone_a and tone_b, and cannot be determined differently. g. internal data memory for tgen1 fade-out step value control (tgen1_fade_out_st) initial value: 390ah (-1.0db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-out step to -3db: 10^(-3/20)*16384 = 11598d = 2d4eh upper limit : about -6.0db (data: 2000h) lower limit : about -0.1db (data: 3f44h) notice: the value set here are commonly valid for tone_a and tone_b, and cannot be determined differently. h. internal data memory for tgen1 fade-out time control (tgen1_fade_out_tim) initial value: 002bh (43 sync) compute using the following equation when changing the fade-out time. equation: 43db/?fade-out step value?[db] example: in a case with a fade-out step value 2db: 43/2 = 21d = 15h upper limit : 422 sync (data: 01a6h) lower limit : 8 sync (data: 0008h) notice: ?0000h? is prohibited to set. set a fade-out time less than tim_m0 the value set here are commonly valid for tone_c and tone_d, and cannot be determined differently. i. internal data memory for tgen1 total gain fade-out control (tgen1_gain_total_fade_cont) initial value: 0000h (disabled) ?0000h? in this data memory enables a function of total gain fade-in/-out for tx and rx. 0000h: disabled 0001h: enabled notice: the control of this function is commonly valid for tx and rx, and cannot be determined differently.
fedl7074-003-01 ML7074-004 73/98 j. internal data memory for fade-in step value control of tgen1 total gain (tgen1_gain_total_fade_in_st) initial value: 4c10h (+1.5db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-in step to +3db: 10^(3/20)*16384 = 23143d = 5a67h upper limit : about +6.0db (data: 7fffh) lower limit : about +0.1db (data: 40bdh) notice: the value set here are commonly valid for tx and rx, and cannot be determined differently. k. internal data memory for fade-out step value control of tgen1 total gain (tgen1_gain_total_fade_out_st) initial value: 35d9h (-1.5db) compute using the following equation wh en changing the step value, x. equation: 10^(x/20)*16384 example: sets a fade-out step to -3db: 10^(-3/20)*16384 = 11598d = 2d4eh upper limit : about -6.0db (data: 2000h) lower limit : about -0.1db (data: 3f44h) notice: step values can be set differently and parameters set are common to tgen1_txgain_total and tgen1_rxgain_total. l. internal data memory for tgen1 in-execution flag (tgen1_exe_flag) this address becomes ?0001h? when a tone generator is under operation. initial value: 0000h tone signal tgen1 state flag during execution tone signal cr20="00h" tgen1 state flag during execution tgen1_fade_cont = off tgen1_fade_cont = on cr20="00h"
fedl7074-003-01 ML7074-004 74/98 fsk generator (fsk_gen) the fsk generator (fsk_gen) frequency modulates the data set in the control register, and outputs it to vfro0 and vfro1. table 10 lists the specifications of the fsk generator, and figure 31 shows its block diagram. the fsk generator is made up of an fsk signal generation block that allows buffering of up to three words, a register for setting data, and a gain adjustment block. by setting fgen_en (cr2-b6) to ?1?, the fsk genera tor starts operating, and outputs a mark bit (?1?) successively. to start data transmission, set the first transmit data in fgen_d[7:0 ](cr18), and set fgen_flag (cr5-b0) to ?1?. when fgen_flga is set to ?1?, the fsk generator transf ers the transmit data in fgen_d[7:0] to the internal buffer if it has a free space, and clears fgen_flag to ?0?. the data that has been transferred to the internal buffer is then output with st (start bit ?0?) and sp (stop bit ?1?) appended to in the transmit sequence shown in figure 32. when setting the next transmit data, do so when fgen_flag is ?0?. if there is no data waiting to be tr ansmitted in the internal buffer of the fgen signal generation block, a mark bit (?1?) is successively transmit ted. the internal buffer of the fsk signal generation block has a 3-stage structure; it can buffer data of up to 4 words including the fsk output data setup register fgen_d[7:0]. to end transmission, set fgen_en to ?0? while fgen_flag is ?0?. if the transmission of the data that is set in fgen_d[7:0] is completed before fgen_en is set to ?0?, the fsk generator stops. if fgen_en is set to ?0? while the fsk generator transmits a mark bit (?1?) successively, and if there is no data waiting to be transmitted, the fsk generator stops after outputting a mark bit (?1?) for a maximum of 1-bit period. figure 33 shows the transmit and stop timings, and figure 34 shows an example of control. in addition, the output level of the fsk generator ca n be changed by fgen_gain (internal data memory). table 10 specifications of fsk generator modulation method frequency modulation synchronization start-stop transfer speed 1200 bps 1300 hz (data ?1? mark) output frequencies 2100 hz (data ?0? space) output data setting register 8 bits (cr18-b[7:0]) output level ?13.3 dbm0 (initial value, gain adjustment possible) fig. 31 fsk generator block diagram fig. 32 data transmit sequence fgen_gain cr2-b6(fgen_en) cr5-b0(fgen_flag) cr18 (fgen_d[7:0]) fgen_d<7:0> buff1 fskgen buff0 buff_out 0 1 2 3 4 5 6 7 s p s t transmit direction fgen_d st:startbit("0") sp:stop bit("1")
fedl7074-003-01 ML7074-004 75/98 fig. 33 fsk data transmit and stop timings (when transmitting 50 bits) note: when the fsk generator is operating, it is recommended to k eep the other detector sections deactive so that they do not cause to generate an interrupt. vfro fgen_flag intb pin output fgen_en fgen_d[7:0] setting timing . . . . . . mark("1") continuous output t1 mark("1") continuous output t2 t3 t4 t5 10-bit output period . . . . . . t1 . . . . 10-bit output period . . . . . . t2 10-bit output period . . . . . . t3 10-bit output period . . . . . . t4 10-bit output period . . . . . . t5
fedl7074-003-01 ML7074-004 76/98 fig. 34 fsk output control method a. internal data memory for fsk gain adjustment (fgen_gain) initial value: 0080h the output level of the initial value will be ?13.3 dbm0. compute the setting value using the following equation when changing the output level. equation: 0080h ? gain example: for decreasing the output level by 6 db. 0080h ? 0.5 = 0040h upper limit: 40 db higher (data: 3200h) lower limit: 40 db lower (data: 0001h) notice: the maximum amplitude should not exceed 1.3vp-p. fgen start(cr2-b6="1") mark("1")transmitted continuously? no final data? yes yes fgen stop (cr2-b6="0") fgen_flag (cr5-b0)=0? yes transmit data setting (cr18) fgen_flag(cr5-b0)=1 no fgen_flag (cr5-b0)=0? yes no no
fedl7074-003-01 ML7074-004 77/98 tone0 detector (tone_det0) the tone_det0 detector is composed of a main signal detector that detects the signal of the corresponding frequency, noise detector that detects the signals other than the corresponding frequency, and on/off guard timers. the detector detects a 1650 hz single tone signal input from ain0 and ain1 . this detector becomes effective when the control register tdet0_en (cr2-b3) is ?1?. wh en the tone is detected (m ain signal detected and noise not detected), the control register tone0_det (cr3-b3) will be set to ?1 ?. tone0_det will become ?0? when the tone is not detected or when tdet0_en is ?0?. the tone detector can adjust detect time using on/off guard timers and adjust detect level for noise detection. the initial values of both on and off guard timers are 5 ms. the initial values for both main signal detect level and noise detect level are ?5.3 dbm0. the tone detect timing is shown in fig. 35. fig. 35 tone detect timing a. internal data memory for control of th e main signal detect level (tdet0_s_th) initial value: 1ebbh (?5.3 dbm0) compute the setting value using the following equation when changing the detect level x. equation: 10 ((x ? 3.17)/20) ? 2/ ? ? 32768 example: detect level of ?5.3 dbm0. 10 ((?5.3 ? 3.17)/20) ? 2/ ? ? 32768 = 7857d = 1ebbh upper limit :3.17 dbm0 (data: 517ch) : ?5.3 dbm0 (data: 1ebbh) lower limit : ?35 dbm0 (data: 0102h) b. internal data memory for control of the noise detect level (tdet0_n_th) initial value: 1ebbh (?5.3 dbm0) compute the setting value using the following equation when changing the detect level x. equation: 10 ((x ? 3.17)/20) ? 2/ ? ? 32768 example: detect level of ?5.3 dbm0. 10 ((?5.3 ? 3.17)/20) ? 2/ ? ? 32768 = 7857d = 1ebbh upper limit :3.17 dbm0 (data: 517ch) : ?5.3 dbm0 (data: 1ebbh) lower limit : ?30 dbm0 (data: 0102h) write 7fffh to the above-mentioned internal data memory (tdet0_n_th) when stopping the noise detect function. tdet0_en ain input tone signal main signal detection noise detection voice off guard timer intb pin output tone0_det on guard timer tone detect internal signal
fedl7074-003-01 ML7074-004 78/98 c. internal data memory for the detect on guard timer (tdet0_on_tm) initial value: 0028h (5 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) d. internal data memory for the detect off guard timer (tdet0_off_tm) initial value: 0028h (5 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) e. internal data memory for contro lling the detect frequency (tdet0_freq) initial value: ? the detect frequency can be changed. contact rohm's responsible sales person when you wish to change the detect frequency.
fedl7074-003-01 ML7074-004 79/98 tone1 detector (tone_det1) the tone_det1 detector is composed of a main signal detector that detects the signal of the corresponding frequency, noise detector that detects the signals other than the corresponding frequency, and on/off guard timers. the detector detects a 2100 hz single tone signal input from ain0 and ain1 . this detector becomes effective when the control register tdet1_en (cr2-b4) is ?1?. wh en the tone is detected (m ain signal detected and noise not detected), the control register tone1_det (cr3-b4) will be set to ?1 ?. tone1_det will become ?0? when the tone is not detected or when tdet1_en is ?0?. the tone detector can adjust detect time using on/off guard timers and adjust detect level for noise detection. the initial values of both on and off guard timers are 5 ms. the initial values for both main signal detect level and noise detect level are ?5.3 dbm0. the tone detect timing is shown in fig. 36. fig. 36 tone detect timing a. internal data memory for control of th e main signal detect level (tdet1_s_th) initial value: 1ebbh (?5.3 dbm0) compute the setting value using the following equation when changing the detect level x. equation: 10 ((x ? 3.17)/20) ? 2/ ? ? 32768 example: detect level of -5.3 dbm0. 10 ((?5.3 ? 3.17)/20) ? 2/ ? ? 32768 = 7857d = 1ebbh upper limit : 3.17 dbm0 (data: 517ch) : ?5.3 dbm0 (data: 1ebbh) lower limit : ?35 dbm0 (data: 0102h) b. internal data memory for control of the noise detect level (tdet0_n_th) initial value: 1ebbh (?5.3 dbm0) compute the setting value using the following equation when changing the detect level x. equation: 10 ((x ? 3.17)/20) ? 2/ ? ? 32768 example: detect level of ?5.3 dbm0. 10 ((?5.3 ? 3.17)/20) ? 2/ ? ? 32768 = 7857d = 1ebbh upper limit :3.17 dbm0 (data: 517ch) : ?5.3 dbm0 (data: 1ebbh) lower limit : ?30 dbm0 (data: 0102h) write 7fffh to the above-mentioned internal data memory (tdet1_n_th) when stopping the noise detect function. tdet1_en ain input tone signal main signal detection noise detection voice off guard timer intb pin output tone1_det on guard timer tone detect internal signal
fedl7074-003-01 ML7074-004 80/98 c. internal data memory for the detect on guard timer (tdet1_on_tm) initial value: 0028h (5 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) d. internal data memory for the detect off guard timer (tdet1_off_tm) initial value: 0028h (5 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) e. internal data memory for contro lling the detect frequency (tdet1_freq) initial value: ? the detect frequency can be changed. contact rohm's responsible sales person when you wish to change the detect frequency.
fedl7074-003-01 ML7074-004 81/98 dtmf detector (dtmf_rec) this section detects the dtmf signal input from ain. the dtmf detector is made up of a dtmf detection block that detects the dtmf signal, a noise detection block that detects signals other than th e dtmf signal, an on guard timer, and an off guard timer. the dtmf detector becomes effective when the control register dtmf_en (cr2-b2) is ?1?, and when a valid dtmf signal is detected, dtmf_det (cr4-b4) becomes ?1? and the received code is stored in dtmf_0 to dtmf_3 (cr4-b3, 2, 1, 0). when no dtmf signal is detected or when dtmf_en is ?0?, dtmf_det will be ?0? and also dtmf_0 to dtmf_3 will be ?0000?. the dtmf detect timing is shown in fig. 38. the dtmf detector is composed of a detector section, an on guard timer, and an off guard timer. the detect time and the detect level can be adjusted. the initial values of both on and off guard timers are 20 ms. the initial value of the detect level is ?37.0 dbm0. fig. 37 dtmf detect timing a. internal data memory for gain adjustment (dtmf_th) initial value: 1000h (?37.0 dbm0) compute the setting value using the following equation when changing the detect level. equation: 1000h ? 1 / gain example: increasing the detect level by 6 db. 1000h ? 0.5 = 0800h upper limit : 12 db higher (data: 0400h) lower limit : 12 db lower (data: 4000h) note: the detection level set in the above data memory (d tmf_th) is the common detection level of the dtmf detection block and the noise detection block. b. internal data memory for the on guard timer (dtmf_on_tm) initial value: 00a0h (20 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) dtmf_en ain input dtmf signal voice dtmf_det dtmfcode output (dtmf_code[3:0]) "0000" detected code "0000" on guard timer off guard timer intb pin output dtmf detect section noise detect section dtmf detect internal signal
fedl7074-003-01 ML7074-004 82/98 c. internal data memory for the off guard timer (dtmf_off_tm) initial value: 00a0h (20 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) d. internal data memory for noise detection function control (dtmf_ndet_cont) initial value: 0002h (noise detection function enabled) by writing 0000h into this internal data memory, the noise detection function of the dtmf detector is disabled. notice: during dtmf signal detection, if the dtmf signal ch anges to another code successively, the received code changes and an interrupt can be generated with dtmf_det in the ?1? state. note: to use this internal data memory by inputting signals in g.711 coding format from the pcm interface, set the input level of the dtmf signal (per wave) at ?10 dbmo or lower. if the dtmf signal is input at a level greater than?10 dbmo, the dtmf signal may not be detected normally.
fedl7074-003-01 ML7074-004 83/98 echo canceller the block diagram of the echo canceller is shown in fig. 38. the echo canceller has a delay time of 32 ms and is ac tivated by setting a ?1? in ec_en (cr2-b1). the operation setting of the echo canceller is done mainly using the internal data memory locations ec_cr and glpad_cr. fig. 38 echo canceller block diagram a. echo canceller control (ec_cr) iinitial value: 0012h write ?0? in the higher order 8 bits (b15 to b8) b7 b6 b5 b4 b3 b2 b1 b0 thr ? hld hdb clp ? attb ? initial value 0 0 0 1 0 0 1 0 b7: through mode control 1: through mode 0: normal mode (echo cancel operation) when this through mode control bit of the echo canceller is set, the data of rin and sin are output directly to rout and sout while retaining their respect ive echo coefficients. further, duri ng the through mode, the hld, hdb, attb and clp functions are disabled. b6: reserved bit. prohibited to change the initial value. b5: coefficient update control 1: coefficient fixed 0: coefficient updated this bit selects the presence or absence of updating of the adaptive fir filter (aff) coefficient of the echo canceller. this function becomes valid when thr is in the normal mode. echo canceller + - adaptive fir filter(aff) lpad gpad atts attr center clip sin rout sout rin power calc howling detector double talk det
fedl7074-003-01 ML7074-004 84/98 b4: howling detector control 1: off 0: on this bit controls the function of detecting and removing howling which is generated in a hands-free acoustic system, etc. this function becomes valid when thr is in the normal mode. b3: center clip control 1: on 0: off this bit controls the center clip function in which the sout output is forcibly fixed to the minimum positive value when the sout output of the echo canceller is ?57 dbm0 or less. this function becomes valid when thr is in the normal mode. b2: reserved bit. prohibited to change the initial value. b1: attenuator control 1: att off 0: att on this bit selects the switching on/off of the att functio n which prevents howling using the attenuators atts and attr provided at the rin input and sout output of the echo canceller. when only the rin input is present, the attenuator (atts) of sout will be inserted. when only the sin input is present or when both the sin and rin inputs are present, the attenuator (attr) of rin will be inserted. the respective attenuation values are 6 db. this function becomes valid when thr is in the normal mode. b0: reserved bit. prohibited to change the initial value. b. glpad control (glpad_cr) initial value: 000fh this data memory controls the glpad within the echo ca nceller. write ?0? in the higher order 8 bits (b15 to b8). b7 b6 b5 b4 b3 b2 b1 b0 ? ? ? ? gpad2 gpad1 lpad2 lpad1 initial value 0 0 0 0 1 1 1 1 b7, 6, 5, 4: reserved bits. b3, 2: output level control these bits control the gpad level for the echo canceller output gain. (0, 1): +18 db (0, 0): +12 db (1, 1): +6 db (1, 0): 0 db b1, 0: input level control these bits control the lpad level for the echo canceller input loss. (0, 1): ?18 db (0, 0): ?12 db (1, 1): ?6 db (1, 0): 0 db
fedl7074-003-01 ML7074-004 85/98 c. precautions in using the echo canceller c-1 in the echo path, make sure that the echo signal does not cause saturation, waveform distortion, etc., in the external amplifier, etc. the echo attenuation becomes poor if any saturation or waveform distortion occur. c-2 make the settings so that the echo return loss (e.r.l.) is attenuating. further, it is recommended to use the glpad function if the e.r.l. is set to be amplified. the echo attenuation gets deteriorated seriously if the e.r.l. is set to be amplified. the e.r.l. is the attenuation (loss) of echo amount from the echo canceller output (rout) to the echo canceller input (sin). c-3 when the echo path can change (such as during a reconn ected call), it is recommended to carry out a reset using ec_en (cr2-b1), pdnb, or spdn (cr0-b7).
fedl7074-003-01 ML7074-004 86/98 dial pulse detector (dpdet) dial pulse signals input at the general-purpose input pin gpi0 are detected by this dpdet. the dial pulse detector becomes effective when the control register bit dpdet_ en (cr10-b6) is ?1?. dp_det (cr4-b6) becomes ?1? when a dial pulse signal is detected and the detected number of dial pulses is stored in dpdet_code. the number of dial pulses detected should be read out from dpdet_code at the time when dp_det goes from ?1? to ?0?. when a dial pulse signal is not detected, or wh en dpdet_en is ?0?, dp_det will remain ?0?. the dial pulse detect timing is shown in fig. 39. the dial pulse detector samples the dial pulse signal input at gpi0 at 8 khz sampling rate, and detects the dial pulses base d on the settings of the on guard timer (d pdet_on_tim) and off guard timer (dpdet_off_tim). further, it is possible to adjust the detect end time by setting the detect end timer (dpdet_detoff_tim). fig. 39 dial pulse detect timing a. dial pulse detect contro l register (dpdet_en cr10-b6) 0: dial pulse detection stopped 1: dial pulse detection active b. dial pulse detector detect status register (dp_det cr4-b6) 0: dial pulses not detected 1: dial pulses detected this bit is set to ?1? after dpdet_en has been set when an edge at gpi0 is detected. further, if no edge is detected for a period set in dpdet_d etoff_tim after an edge detection, this bit will be cleared automatically to ?0?. gpi0 status of internal detection dpdet_off_tim dpdet_on_tim status of internal detection by guard timer dp detect timing dpdet_en gpi0 (internal signal after masked by guard timer) dp_det dpdet_detoff_tim dpdet_detoff_tim dpdet_code 123 010 intb
fedl7074-003-01 ML7074-004 87/98 c. internal data memory for on guard timer (dpdet_on_tim) iinitial value: 0028h (5 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) d. internal data memory for off guard timer (dpdet_off_tim) initial value: 0028h (5 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 5 ms 5/0.125 = 40d = 0028h upper limit : 4095.875 ms (data: 7fffh) : 5 ms (data: 0028h) lower limit : 0.125 ms (data: 0001h) e. internal data memory for detect polarity control (dpdet_pol) iinitial value: 0000h (no polarity reversal) controls the polarity of the input from gpi0. 0000h: no polarity reversal 0001h: polarity reversal present f. internal data memory for detect end control (dpdet_detoff_tim) initial value: 03e8h (125 ms) use the following equation when changing the timer value. equation: guard timer value in ms/0.125 ms example: 125 ms 125/0.125 = 1000d = 03e8h upper limit : 4095.875 ms (data: 7fffh) : 125 ms (data: 03e8h) lower limit : 0.125 ms (data: 0001h) g. internal data memory for indicating number of detected pulses (dpdet_code) initial value: 0000h (not-detected state) indicates the number of detected pulses. this internal data memory for indication is updated when an edge is detected. notice: ignore the interrupt occurred after the time set by th e on guard timer if the dpd et is activated under the following conditions: ? dpdet_pol = ?0?, gpi0 = ?1? ? dpdet_pol = ?1?, gpi0 = ?0?
fedl7074-003-01 ML7074-004 88/98 dial pulse transmitter (dpgen) the dial pulse transmitter outputs a dial pulse signal at the general-purpose output pin gpo0. the dial pulse generation will be effective when the control memory bit dpge n_en is ?1?, and a dial pulse signal is output with the number of pulses set in dpgen_data. the dial pulse output timing is shown in fig. 40. the spee d (rate) of dial pulses can be selected to be 10pps or 20pps by setting dpgen_pp s accordingly. further, it is possible to adjust the make/break ratio by setting the break duration using dpgen_duty. also, the output polarity of the dial pulse signal can be changed by dpgen_pol. the maks/break ratio can be adzusted by setting the break duration (dpgen_duty) - 10pps/output polarity : posive logic/ 10 output pulses gpo0 dpgen_off_tim dpgen_en - 10pps/output palarity : negative l ogic/ 2 output pulses dpgen_off_tim 0.1sec/10pps (0.05sec/20pps) gpo0 dpgen_en - output polarity setting, maks/break ratio adzustment the output polarity can be changed (dpgen_pol). positive logic negative logic break duration break duration break duration break duration gpo0 gpo0 fig. 40 dial pulse output timing a. internal data memory for dial pulse transmit control (dpgen_en) initial value: 0000h the dial pulses are transmitted when a ?0001h? is written in this data memory. this data memory will be cleared automatically after a period of time set in dpgen_off_tim. 0000h: dial pulse output stopped 0001h: dial pulse output active notice: activate dpgen with cr17-b0 (gpo0) being in the ?0? st ate, according to the setting of internal of data memory for output polarity control (dpgen_pol). dpgen_pol =0000h (positive logic) : cr17-b0 (gpo0) = ?0? dpgen_pol =0001h (negative logi c) : cr17-b0 (gpo0) = ?1?
fedl7074-003-01 ML7074-004 89/98 b. internal data memory for setting the number of pulses (dpgen_data) initial value: 0000h upper limit: 10 (data: 000ah) lower limit: 1 (data: 0001h) c. internal data memory for dial pulse rate control (dpgen_pps) initial value: 0000h 0000h: 10 pps 0001h: 20 pps d. internal data memory for controlling make/break ratio (dpgen_duty) initial value: 0108h (33 ms/10 pps, 16.5 ms/20 pps) use the following equation when setting the ?break? duration. the value will be half this set value in the case of 20 pps. equation: ?break? output time duration in ms/0.125 ms example: 33 ms 33/0.125 = 264d = 0108h upper limit : 100 ms (data: 0320h) : 33 ms (data: 0108h) lower limit : 0.125 ms (data: 0001h) e. internal data memory for end of output control (dpgen_off_tim) initial value: 03e8h (125 ms) use the following equation when setting the end of output control. equation: end of output time duration in ms/0.125 ms example: 125 ms 125/0.125 = 1000d = 03e8h upper limit : 4095.875 ms (data: 7fffh) : 125 ms (data: 03e8h) lower limit : 0 ms (data: 0000h) f. internal data memory for output polarity control (dpgen_pol) initial value: 0000h controls the polarity of output from gpo0. setup value: 0000h ? ? ? ? positive logic (low: make segm ent, high: break segment) setup value: 0001h ? ? ? ? negative logic (low: break segment, high: make segment)
fedl7074-003-01 ML7074-004 90/98 timer (timer) this is a 16-bit up-counter timer. when a ?0001h? is se t in the internal memory for timer control (tim_en), the timer starts counting up the timer count (tim_count) at every 125 ? s. when the timer count value becomes equal to the timer data value, the ti mer counter value will be reset to ?00 00h? and the timer starts counting up again. a. internal data memory for timer control (tim_en) iinitial value: 0000h the timer starts counting up when ?0001h? is written in this data memory location. when a ?0000h? is set here, the counting up will be stopped and the counter value will be cleared. 0000h: stops counting 0001h: starts counting b. internal data memory for timer count indication (tim_count) initial value: 0000h c. internal data memory for timer data (tim_data) initial value: ffffh upper limit : 8192 ms (data: ffffh) lower limit : 0.250 ms (data: 0001h)
fedl7074-003-01 ML7074-004 91/98 outband control (outband_control) this is a function is automatically to mute or to write s ilence data in tx buffer when corresponding detection bit (***_det) gets ?1?. either to mute or to write silence data in tx buffer differs among speech codec?s as shown below; g.711 ( ? -/a-law) mutes speech data given to codec g.729.a writes silence data (80 bits) in tx buffer the 80 bits meaning silence in g.72 9.a to write in tx buffer as default could be altered any 80 bits you like in the initial mode. initial value : 0000h b7 b6 b5 b4 b3 b2 b1 b0 ? ? ? ? ? tdet1 _ob_en tdet0 _ob_en dtmfdet _ob_en initial value 0 0 0 0 0 0 0 0 b7, 6, 5, 4, 3 : reserved bits b2 : tdet1_outband_en control 1 : on (mutes speech data given to codec when tdet1_det is ?1?) 0 : off b1 : tdet0_outband_en control 1 : on (mutes speech data given to codec when tdet0_det is ?1?) 0 : off b0 : dtmfdet_outband_en control 1 : on (writes data specified by outband_ g729_dat which is silence as default when dtmf_det is ?1?) 0 : off - leak time of tones to tx buffer a referential equation for leak time of tones to tx buffer with each speech codec is shown below; g.711 0ms + a + b g.729.a -10ms to -20ms + a + b * -10ms to -20ms by prediction and framing process a : detection delay time of a given detector (ms) depends upon input level, frequency, etc.. b : on-guard timer time of a given detector < example> if the detect delay time of a detector is about 30 ms and the on-guard timer time of a detector is 20 ms, the leak time to the tx buffer is shown below. g.711 30ms (a) + 20m s (b) = approx. 50ms g.729.a (-10ms to -20ms) + 20ms (a) + 20ms (b) = approx. 30ms to 40ms outband g.729.a data (outband_g729_dat) when outband control is made in g.729.a mode, the data in the addresses below are written into tx buffer when corresponding detection bit (***_det) gets ?1?. the data to write into tx buffer could be altered in the initial mode. address: 00a6h 00a7h 00a8h 00a9h 00aah initial value: 7852h 80a0h 00fah c200h 07d6h
fedl7074-003-01 ML7074-004 92/98 lsi code indication (ml7074_version) the code ML7074-004 is indicated here. value: 0003h
fedl7074-003-01 ML7074-004 93/98 example of configuration analog i/f mode echo canceller dtmf_rec + - aff d/a lpf g.729.a tone_gen0 (tonea/b) tx buffer0 rx buffer0 frame/dma controller intb a0-a7 control register 8b d0-d15 16b vref csb rdb wrb fr0b fr1b ack0b ack1b ain1n gsx1 vfro0 avref osc power pll speech codec 10k ? 10k ? dvdd2 dgnd2 avdd agnd pdnb tst1 xi xo g.711 txgain rxgain dvdd1 dgnd1 dvdd0 dgnd0 tst2 tst3 ckgn mck sync(8khz) lpad gpad atts attr bus control unit center clip encoder g.729.a g.711 decoder dtmf_det int dtmf_det tx buffer1 rx buffer1 ain0n gsx0 10k ? ain0p linear pcm codec vfro1 10k ? stgain sync bclk pcmi pcmo tone_det1 tone1_det s/p p/s serial i/f tone0_det tone1_det gpi0 gpi1 gpo0 gpo1 tone_det0 tone0_det fsk_gen tst0 clksel amp0 amp1 amp2 amp3 sin rout sout rin a/d bpf codec dpgen dpdet cr16-b0(gpi0) cr17-b0(gpo0) dp_det dp_det timer dtmf_code[3:0] dtmf_code[3:0] tone_gen1 (tonec/d) g.711 encoder g.711 decoder fgen_flag fgen_flag function stopped cannot be used example of settings in the initialization mode ? cr15 = 40h * this is mandatory. ? cr6=0fh,cr7=ffh,cr8=00h,cr9=01h,cr1= 80h (address : 0fffh, data : 0001h) * this is mandatory. as for how to set them, refer to method of accessing and controlling internal data memory. ? cr11 = 00h (frame/10 ms/16b/speech codec = g.729.a) ? various settings ? cr0 = 09h (ope_stat = ?1?)
fedl7074-003-01 ML7074-004 94/98 pcm i/f mode echo canceller dtmf_rec + - aff d/a lpf g.729.a tone_gen0 (tonea/b) tx buffer0 rx buffer0 frame/dma controller intb a0-a7 control register 8b d0-d15 16b vref csb rdb wrb fr0b fr1b ack0b ack1b ain1n gsx1 vfro0 avref osc power pll speech codec 10k ? 10k ? dvdd2 dgnd2 avdd agnd pdnb tst1 xi xo g.711 txgain rxgain dvdd1 dgnd1 dvdd0 dgnd0 tst2 tst3 ckgn mck sync(8khz) lpad gpad atts attr bus control unit center clip encoder g.729.a g.711 decoder dtmf_det int dtmf_det tx buffer1 rx buffer1 ain0n gsx0 10k ? ain0p linear pcm codec vfro1 10k ? stgain sync bclk pcmi pcmo tone_det1 tone1_det s/p p/s serial i/f tone0_det tone1_det gpi0 gpi1 gpo0 gpo1 tone_det0 tone0_det fsk_gen tst0 clksel amp0 amp1 amp2 amp3 sin rout sout rin a/d bpf codec dpgen dpdet cr16-b0(gpi0) cr17-b0(gpo0) dp_det dp_det timer dtmf_code[3: 0] dtmf_code[3:0] tone_gen1 (tonec/d) g.711 encoder g.711 decoder function stopped cannot be used fgen_flag fgen_flag examples of settings in the initialization mode ? cr15 = 40h * this is mandatory. ? cr6=0fh,cr7=ffh,cr8=00h,cr9=01h,cr1= 80h (address : 0fffh, data : 0001h) * this is mandatory. as for how to set them, refer to method of accessing and controlling internal data memory. ? ? cr10 = 00h (vfro1 = avref/vfro0 = avref) ? cr11 = 00h (frame/10 ms/16b/pcmif = 16-bit linear) ? cr12 = 01h (speech codec = g.729.a/pcmif_en = ?1?) ? various settings ? cr0 = 29h (afe_en = power down/long/ope_stat = ?1?)
fedl7074-003-01 ML7074-004 95/98 example of application circuit 49 avref vfro0 vfro1 avdd 50 51 52 53 54 55 56 57 58 59 60 61 62 63 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 tst3 tst2 dgnd2 xi xo dvdd2 ain1n gsx1 ain0p ain0n gsx0 agnd ml7074 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dgnd0 tst1 tst0 pcmo pcmi bclk sync rdb wrb csb fr0b fr1b dvdd0 intb ack0b ack1b 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dgnd1 dvdd1 a0 a1 a2 a3 a4 a5 a6 a7 gpi0 gpi1 gpo0 gpo1 pdnb clksel d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 64 +3.3v +3.3v +3.3v open open open power down control mcu i/f general- purpose input pins 4.096 mhz crystal oscillator analog input pcm i/f analog output conditions: - when using analog interface - frame mode - sync and bclk are output (clksel="1") general- purpose output pins 16 1.4v
fedl7074-003-01 ML7074-004 96/98 package dimensions qfp64-p-1414-0.80-bk mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 0.87 typ. 5 rev. no./last revised 6/feb. 23, 2001 notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humi dity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl7074-003-01 ML7074-004 97/98 revision history page document no. date previous edition current edition description fedl7074-004-01 nov. 12, 2003 ? ? final edition 1
fedl7074-003-01 ML7074-004 98/98 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, pleas e be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peri pheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended on ly to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or othe r rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatso ever for any dispute arising from the use of such technical information. the products specified in this docu ment are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe design s. lapis semiconductor shall bear no responsibility whatsoever for your use of any produc t outside of the prescribed scope or not in accordance w ith the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malf unction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety devi ce). lapis semiconductor shall bear no responsibility in any way for use of any of the prod ucts for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you w ill be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

▲Up To Search▲

Price & Availability of ML7074-004

	To Download ML7074-004 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .